Stanford Research Systems DS345, Manual

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DS345 Circuitry
8-4
TOP PC BOARD
RIBBON CABLE, ADCs, and DACs (SHEET 1 OF 7)
JP100 and JP101 are the system interface and top board power supply con-
nectors to the bottom board, respectively. U109A is half of a 12-bit DAC that
is used to generate analog voltages for system control. The current output of
the DAC is converted to voltage and level shifted by op-amp U110 to a +/-
5.5 volt range. Five multiplexed (sampled and held) voltages are made avail-
able from MUX U100 and sample/hold buffers U107A-D and U111A.
System A to D conversion is accomplished by successive approximation, us-
ing the system DAC voltage at the output of U110B as the comparison refer-
ence. The voltage to be converted is compared to the DAC output by U102
and the compare result is sent to the system processor on the bottom board.
One of eight analog voltages to be converted is selected by U103 and pre-
sented to sample-and-hold capacitor C113 and buffer U108A.
U104 generates port strobes to be used on the top PCB.
CLOCKS (SHEET 2 OF 7)
The main system clock source is a 40 MHz varactor-tuned crystal oscillator.
The oscillator configuration is a Butler emitter follower consisting of Q203,
crystal X200, and tank circuit L204/L205 and C202, C208, and the varactor
U201. The emitter follower configuration provides the low impedance of the
emitter to drive the crystal, and the capacitive tap into the tank circuit pro-
vides a high impedance at the transistor base. The resonant frequency of
the oscillator is fixed at the third harmonic of the crystal primarily by L204/
L205 and C202. R233 keeps the Q of the tank low enough to avoid spurious
oscillation off the crystal resonance. The crystal drive amplitude is fixed by
an AGC circuit consisting of detector D207 and buffer U205. The current
through Q203 is controlled by U205 based on the output amplitude across
the L203/C204 tank. This signal is discriminated by comparator U200 which
provides the 40 MHz differential ECL clock used throughout the system.
The ECL output of comparator U200 is sent directly to the waveform DAC
clock inputs. This is to ensure that the clock at the DAC is very pure, as the
quality of the DDS output is a direct reflection of the purity of the clock used
for the DAC. The rest of the system uses TTL clocks that are provided by
ECL to TTL converters U209A and U209B. U208, a FAST octal buffer, is
used to delay the TTL clock in 3-5 ns steps in order to provide variable clock
timing for the DDS DAC data latches and the DDS ASIC.
U405B divides the 40 MHz by two to generate the 20 MHz clock used for the
system microprocessor. This signal is also sent to counter U202 to generate
the system 2.5 and 10 MHz, as well as the 1.25 MHz output to drive the sam-
pling phase detector used to lock the unit to an external clock source.
U207 buffers the 10 MHz output which is coupled to the rear-panel 10 MHz
output via tuned circuit L206 and C219 and transformer T202. U207 also
buffers the input signals from either the optional internal oscillator (at pin 12),
or an external input at J201, before the signals pass to the sampling gate