Stanford Research Systems DS345, Manual

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DS345 Circuitry
8-5
U206.
The sampling phase detector is made up primarily of U206. The selected in-
put at U206 pin 1 or 13 is chopped by the RCO output of U202, which serves
as a sampling gate. The gated output at pin 4 is then filtered by R235, C220,
R236 and C221 to form a control voltage to be presented to the oscillator va-
ractor. The nominal system tuning is accomplished by the system DAC volt-
age via R248. D210 clamps the varactor voltage range to near ground.
The external timebase input and the optional internal oscillator inputs are dis-
criminated by ECL converters U209C and U209D, respectively. An external
input is sensed by the voltage at the R245/C225 junction.
DDS ASIC AND MEMORY (SHEET 3 OF 7)
The DDS ASIC, U300, is the heart of the DDS process. The DDS ASIC is to
generates the addresses for the external waveform and modulation RAM,
along with a few control bits. The DDS process works essentially by storing
a sine table in the waveform RAM and then stepping the RAM addresses in
order to output the sine values to a DAC which creates the analog output.
The modulation RAM serves a similar purpose, except it contains data and
opcodes which control the internal registers in the ASIC to accomplish modu-
lation of the output. U302 is the modulation RAM transceiver, and interfaces
the system processor's buffered data bus to the ASIC and modulation RAMS.
U303 and U304 serve a similar purpose for the waveform RAMS. U312,
U313, and U313 are glue logic to control writes and chip enables, etc..
Three external chip select outputs from the ASIC, -WR_EXT0, 1, and 2 con-
trol the writing of modulation data to DACS for output amplitude control, and
a modulation output "mimic".
AMPLITUDE AND SWEEP DACS (SHEET 4 OF 7)
U401 is the modulation mimic output DAC, and generates an analog repre-
sentation of the modulation being used. This is necessary because wave-
form modulation is handled digitally in the ASIC, so no analog modulation
waveforms are actually used. U412A performs fast amplitude control (modu-
lation) based on DDS modulation data. The analog output of this DAC, after
being converted to a voltage output by op-amp U410A, is filtered by the 7th
degree Bessel anti-aliasing filter connected to U410B pin 7. This filter en-
sures that frequencies higher than 50 kHz do not appear in the modulation
control output. 12-bit DAC U109B provides the reference input to DAC
U412A, which is multiplied in U412A to set the system amplitude output. For
external amplitude control, an analog voltage b/- 5 volts at rear pan-
el input J402 provides the reference to U109B after being buffered by
U417A. R428 pulls this input to the 5 volt reference when an external signal
is not present.
The 5th degree Bessel filter at the output of U406A pin 1 performs the anti-
aliasing function for the modulation mimic output. U409 selects the outputs
that are presented to the SWEEP OUT and MOD OUT rear panel BNCs, as
well as the test signal applied to the system ADC input from U409 pin 4.