Stanford Research Systems DS345, Manual

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Introduction
2-2
through the entire waveform RAM changes, thus changing the output fre-
quency.
Frequency changes now can be accomplished phase continuously in only
one clock cycle. And the fixed clock eliminates phase jitter and requires only
a simple fixed frequency anti-aliasing filter at the output.
The DS345 uses a custom Application Specific Integrated Circuit (ASIC) to
implement the address generation in a single component. The frequency res-
olution is equal to the resolution with which the Phase Increment can be set.
In the DS345, the phase registers are 48 bits long, resulting in an impressive
1:10
14
frequency resolution. The ASIC also contains a modulation control
CPU that operates on the Phase Accumulator, Phase Increment, and exter-
nal circuitry to allow digital synthesis and control of waveform modulation.
The Modulation CPU uses data stored in the Modulation RAM to produce
amplitude, frequency, phase, and burst modulation, as well as frequency
sweeps. All modulation parameters, such as rate, frequency deviation, and
modulation index, are digitally programmed.
DDS gives the DS345 greater flexibility and power than conventional synthe-
sizers or arbitrary waveform generators without the drawbacks inherent in
PLL designs.
DS345 Description
40MHz Clock
DDS345 ASIC
Modulation RAM
Waveform
RAM
12 bit
DAC
10 MHz Bessel Filter
Cauer Filter x2
Amplitude DAC
Amplitude
Control Output
Amp
Attenuators
Function
Output
Square Wave
Comparator
Sync
Output
AM Input
Figure 2: DS345 Block Diagram
A block diagram of the DS345 is shown in Figure 2. The heart of the DS345
is a 40 MHz crystal clock. This clock is internally provided, but may be phase
locked to an external reference. The 40 MHz clock controls the DDS345
ASIC, waveform RAM, and high-speed 12bit DAC. Sampling theory limits
the frequency of the waveform output from the DAC to about 40% of 40 MHz,
or 15 MHz. The 48 bit length of the DDS345's PIR's sets the frequency reso-
lution to about 146 nHz. These parameters and the DAC's 12 bit resolution
define the performance limits of the DS345.