Spectrum Digital TMS320DM642, Technical Reference

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Spectrum Digital, Inc
2-10 TMS320DM642 EVM Technical Reference
2.2.5 Audio PLL/VCXO Circuit/PLL1708 Clock Generator
The DM642 EVM implements a multiple PLL clock generator for creating the Audio
clocks for the board.
In streaming video applications the audio and video sequences can lose
synchronization. The DM642 uses a VCXO interpolation circuit to incrementally speed
up or slow down the STCLK input to allow for this synchronization to remain locked.
The STCLK is used to implement this feature and is created by the DM642’s VDAC pin
during a PICX100-27W Voltage Controlled Oscillator. The VDAC pin is controlled via
internal DM642 registers.
The STCLK is also a source clock for the PLL1708 programmable PLL device. This
device creates the clocks for the AIC23B Codec, SPDIF, daughter card STCLK and
optional encoder clocking.
The PLL1708 is programmable via the PLL Data Register in the FPGA which serializes
the user data to the proper format required by the PLL1708.
The diagram below is a simplified diagram of this clocking scheme.
DM642
VCXO
Circuit Using
PICX100-27
PLL1708
SCK03
SCK02
MCK02
MCK01
XT1
VDAC STCLK
P
L
L
M
S P
L
L
M
C P
L
L
M
D
AIC23_STCLK
DM642_AHCLKX0
DC_STCLK
SAA7105_STCLK
To FPGA
Figure 2-3, Audio PLL/VCXO Circuit/PLL1708 Clock Generator
STCLK