Spectrum Digital TMS320DM642, Technical Reference

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Spectrum Digital, Inc
2-3
Strapping resistors R119, R121, R122, and R123 set the inputs for the S0, S1 inputs on
the PLL.
The DM642 can be configured as the source of the EMIF clock. The ECLKIN pin is the
default on the EVM. However it is possible to operate the EMIF clock as a divider
function of the CPU clock. This configuration is done at reset via the ECLKINSEL0 and
ECLKINSEL1 pins which are shared with the EMIF address pins EA19, and EA20. The
table below shows this configuration.
* Default
Table 3: EMIF Interfaces
ECLKINSEL0 ECLKINSEL1 Mode
0 0 ECLKIN *
0 1 CPUCLK/4
1 0 CPUCLK/6
1 1 ECLKIN