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3-21

3.5 Reset Switch - S3

There are three sources for reset on the TMS320DM642 EVM. The first reset is the
power on reset. This circuit waits until power is within the specified range before
releasing the power on reset pin to the TMS320DM642.

The second source is the push button Reset switch, S3. When this button is pressed
the EVM is put through the reset state.

There is also an optional 2 pin Reset header, JP1, which is connected in parallel to the
Reset switch, S3. When this header is shorted the EVM is put into reset

3.6 Test Points

TheTMS320DM642 EVM has 23 test points. Their position are shown in the figure
below.

Figure 3-17, TMS320DM642 EVM Test Points

TP6

TP5

TP3

TP9

TP1

TP13

TP14 TP15 TP11

TP8

TP21 TP22 TP23

TP20 TP18 TP12 TP17

TP19

TP4

TP10

TP2

TP16

TP7

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Summary of Contents for TMS320DM642

Page 1: ...TMS320DM642 Evaluation Module with TVP Video Decoders 2004 DSP Development Systems Reference Technical ...

Page 2: ......

Page 3: ... With TVP Video Decoders Technical Reference 507345 0001 Rev B December 2004 SPECTRUM DIGITAL INC 12502 Exchange Drive Suite 440 Stafford TX 77477 Tel 281 494 4505 Fax 281 494 5310 sales spectrumdigital com www spectrumdigital com ...

Page 4: ...y for applications assistance customer product design software performance or infringement of patents or services described herein Nor does Spectrum Digital warrant or represent any license either express or implied is granted under any patent right copyright or other intellectual property right of Spectrum Digital Inc covering or relating to any combination machine or process in which such Digita...

Page 5: ...erface 2 4 2 1 3 UART Interface 2 5 2 1 4 FPGA Asynchronous Memory Interface 2 5 2 1 5 FPGA Synchronous Memory Interface 2 6 2 1 6 EMIF Buffer Decoder Control 2 6 2 2 Video Port McASP Interfaces 2 7 2 2 1 Video Decoder Ports 2 7 2 2 2 Video Encoder Ports 2 7 2 2 3 FPGA Video Functions 2 8 2 2 4 AIC23B Interface 2 9 2 2 5 Audio PLL VCXO Circuit PLL1708 Clock Generator 2 10 2 3 PCI HPI Ethernet Inte...

Page 6: ...put Connector 3 11 3 2 13 J14 Audio Line Output Connector 3 12 3 2 14 J15 Capture Port 1 Video Input Connector 3 12 3 2 15 J16 Capture Port 1 S Video Input Connector 3 13 3 2 16 J17 Capture Port 1 Composite Video Input Connector 3 13 3 2 17 J18 Capture Port 2 Composite Video Input Connector 3 14 3 2 18 J19 60 Pin Emulation Connector 3 14 3 2 19 J20 P2 PCI Connector 3 15 3 2 20 DC_P1 Video Port 2 E...

Page 7: ...ute on board or expand the system in a variety of ways Notational Conventions This document uses the following conventions The DM642 Evaluation Module will sometimes be referred to as the DM642 EVM or EVM Program listings program examples and interactive displays are shown in a special italic typeface Here is a sample program listing equations rd strobe rw Information About Cautions This book may ...

Page 8: ...df TMS320C6000 DSP Multichannel Audio Serial Port McASP Reference Guide spru175a pdf TMS320C6000 DSP Inter Integrated Circuit I2C Module Reference Guide spru190d pdf TMS320C6000 Peripherals Reference Guide spru295 pdf TMS320DM642 EVM OSD FPGA User s Guide spru610 pdf TMS320C64x DSP Two Level Internal Memory Reference Guide spru628 pdf TMS320C6000 DSP Ethernet Media Access Controller EMAC Managemen...

Page 9: ...Table 1 Manual History Revision History A Production Release B Updated for HD Filters Table 2 Board History Revision History A Prototype Release B Production Release ...

Page 10: ......

Page 11: ...es a description of the TMS320DM642 EVM along with the key features and a block diagram of the circuit board Topic Page 1 1 Key Features 1 2 1 2 Functional Overview 1 3 1 3 Basic Operation 1 4 1 4 Memory Map 1 5 1 5 Configuration Switch Settings 1 6 1 6 Power Supply 1 7 ...

Page 12: ...ts with 2 on board decoders and 1 on board encoder 32 Mbytes of synchronous DRAM On Screen display OSD via FPGA 4 Mbytes of non volatile Flash memory AIC23B stereo codec Ethernet interface Software board configuration through registers implemented in FPGA Configurable boot load options JTAG emulation through on board external emulator interface Figure 1 1 Block Diagram DM642 EVM PWR MIC IN LINE IN...

Page 13: ...e input line input and line output The codec can select the microphone or the line input as the active input The analog output is driven to the line out fixed gain connector The McASP can be re routed to the expansion connectors in software A programmable gate array called an FPGA is used to implement glue logic that ties the board components together The FPGA also has a register based software us...

Page 14: ...nt Code Composer communicates with the board through an external JTAG emulator To start follow the instructions in the Quick Start Guide to install Code Composer This process will install all of the necessary development tools documentation and drivers Detailed information about the EVM including examples and reference material is available on the EVM s CD ROM ...

Page 15: ...d RAM The EMIF External Memory Interface has 4 separate addressable regions called chip enable spaces CE0 CE3 The SDRAM occupies CE0 while the Flash UART and FPGA are mapped to CE1 Daughter cards use CE2 and CE3 CE3 is configured for synchronous operation for on screen display functions and other synchronous registers implemented in the external FPGA Internal Memory Cache DM642 EVM Reserved or Per...

Page 16: ...of 8 bit Flash in little endian mode The table below shows the settings for switch S1 Configuration switch 2 controls the endianness of the DSP and PCI ROM enable The tables below shows the settings for switch S2 Default as shipped configuration Table 1 Configuration Switch S1 Settings S1 2 S1 1 Configuration Description Off Off No Boot Off On HPI PCI Boot On Off Reserved On On EMIF boot from 8 bi...

Page 17: ...the board The power connector is a 2 5mm barrel type plug LDO voltage regulators are used to generate the FPGA core voltage and video input and output voltages There are five power test points on the EVM at TP4 TP8 TP13 TP15 and TP16 These test points provide a convenient mechanism to check the EVM s multiple power supplies The table below shows the voltages for each test point and what the supply...

Page 18: ...Spectrum Digital Inc 1 8 TMS320DM642 EVM Technical Reference ...

Page 19: ...er Decoder Control 2 6 2 2 Video Port McASP Interfaces 2 7 2 2 1 Video Decoder Ports 2 7 2 2 2 Video Encoder Port 2 7 2 2 3 FPGA Video Functions 2 8 2 2 4 AIC23B Interface 2 9 2 2 5 Audio PLL VCXO Circuit PLL1708 Clock Generator 2 10 2 3 PCI HPI Ethernet Interfaces 2 11 2 3 1 PCI Interface 2 11 2 3 2 PCI EEPROM Interface 2 11 2 3 3 Ethernet Interface 2 12 2 3 4 HPI Interface 2 12 2 4 I2C Interface...

Page 20: ... This 32 megabyte SDRAM space is used for program data and video storage The bus uses an external PLL device to operate the SDRAM at 133 megahertz for optimal performance Refresh for SDRAM is handled automatically by the DM642 The PLL used for the EMIF is a ICS512 The input clock to this PLL is 25 Megahertz The table below shows the available frequencies using the 25 Megahertz input clock Default ...

Page 21: ...s the default on the EVM However it is possible to operate the EMIF clock as a divider function of the CPU clock This configuration is done at reset via the ECLKINSEL0 and ECLKINSEL1 pins which are shared with the EMIF address pins EA19 and EA20 The table below shows this configuration Default Table 3 EMIF Interfaces ECLKINSEL0 ECLKINSEL1 Mode 0 0 ECLKIN 0 1 CPUCLK 4 1 0 CPUCLK 6 1 1 ECLKIN ...

Page 22: ... The memory address space available in CE1 space is smaller than the size of the Flash so the FPGA is used to create 3 extended page address lines These extended address lines are addressable via the FPGA Flash Base Register and default to 000 binary at Reset The addresses and pages are shown in the table below Table 4 Flash Memory Interface Address Range Page Number Contents 0x9000 0000 0x9007 FF...

Page 23: ...ed below More information is available on these registers in the TMS320DM642 EVM OSD FPGA User s Guide SPRU295 The addresses and registers are shown in the table below Table 5 UART Addresses UART Address A 0x9008 0000 0x9008 0007 B 0x9008 0008 0x9008 000F Table 6 FPGA Asynchronous Memory Interface Address Function R W Bits 0x9008 0010 OSD Control Register R W 6 0x9008 0011 DMA Threshold LSB Regist...

Page 24: ...he VHDL is shown below FLASH_CE 0 when A22 0 and CE1 0 else 1 UART_CSA 0 when A22 1 and A8 0 and A7 0 and A6 0 and CE1 0 else 1 UART_CSB 0 when A22 1 and A8 0 and A7 0 and A6 1 and CE1 0 else 1 EMIF_OE 0 when CE1 0 or CE2 0 or CE3 0 else 1 EMIF_DIR 1 when CE1 0 and AOE 0 or CE2 0 and AOE 0 or CE3 0 and AOE 0 else 0 Table 7 FPGA Synchronous Memory Interface Address Function R W Bits 0xB000 0000 Syn...

Page 25: ...din connector J16 The input should be a composite video source such as a DVD player or a video camera The decoders are programmable via the DM642 s I2 C bus and can interface to all major composite video standards such as NTSC PAL and SECAM by appropriately programming the internal registers in the decoder 2 2 2 Video Encoder Port The DM642 s Video Port 2 is used to drive the video encoder It is r...

Page 26: ...2 s Video Port 2 to the Phillips SAA7105 Video Encoder For HDTV the FPGA provides enhanced clocking and for on screen display functions the FPGA has FIFOs to mix the Video Port 2 data with the data from these internal FIFOs The FIFO s in the FPGA are accessed via the DM642 s EMIF in synchronous mode via the CE3 space For more information on the implementation of the FPGA functions the user should ...

Page 27: ...ts are supported based on the three variables of sample width clock signal source and serial data format The EVM examples generally use a 16 bit sample width with the codec in master mode so it generates the frame sync and bit clocks at the correct sample rate without effort on the DSP side The preferred serial format is DSP mode which matches the McASP s burst mode The codec has a programmable cl...

Page 28: ...pin during a PICX100 27W Voltage Controlled Oscillator The VDAC pin is controlled via internal DM642 registers The STCLK is also a source clock for the PLL1708 programmable PLL device This device creates the clocks for the AIC23B Codec SPDIF daughter card STCLK and optional encoder clocking The PLL1708 is programmable via the PLL Data Register in the FPGA which serializes the user data to the prop...

Page 29: ...supports an external EEPROM which holds optional PCI configuration values when enabled The EEPROM is enabled from configuration switch S2 When S2 1 is on the PCI configuration uses the EEPROM parameters for configuration If S2 1 is off the internal DM642 default registers are used for configuration The table below shows the contents of the EEPROM when shipped from the factory Table 8 EEPROM Memory...

Page 30: ...ultiplexed accesses The EVM supports Host Port Interface accesses via the PCI Connector The signals for the DM642 s HPI port are brought out to the PCI connectors and the user can interface to them via these connectors The table in Section 3 enumerates the signals used for HPI accesses The EVM automatically enables the EMAC when the EVM is not inserted into a PC Furthermore it drives the PCI_EN pi...

Page 31: ...can be configured to operate as a SPDIF transmitter The DM642 EVM supports a single SPDIF output which is routed to RCA jack J9 The SPDIF output pin is routed to a driver and filter circuit When the SPDIF interface is enabled the TLV320AIC23B codec is disabled Table 9 I2 C Memory Map Device Address R W Function TVP5146 0xBA R W Capture 1 Decoder TVP5150A 0xB8 R W Capture 2 Decoder SAA7105 0x88 R W...

Page 32: ... access to the DSP s EMIF signals to interface with memories and memory mapped devices It supports byte addressing on 32 bit boundaries The signals on this bus are buffered The video ports are brought out to the daughter card interface Four signals are used to disable the on board video peripherals so that they can be used by the expansion connector The table below indicates the operation of these...

Page 33: ... Megahertz oscillator to generate the input clock CLKIN The DM642 has an internal PLL which can multiply the input clock to generate the internal clock The PLL multiplier is set via the CLKMODE0 and CLKMODE1 pins on the DM642 device At reset these pins are sampled and this determines the PLL multiplier for the internal CPU clock The strapping of these pins is done with discrete resistors on the EV...

Page 34: ... procedure The figure below indicates the position of the components to be modified The sequence to update the EVM is 1 Remove C133 C162 and C221 Replace with 560pF capacitors 2 Remove C132 C161 and C220 Replace with 390pF capacitors 3 Remove L10 L15 and L24 Replace with 2 2uH inductors 4 Remove L14 L19 and L23 Replace with 2 2uH inductors 5 Install 120pF capacitors at C341 C342 and C343 The table...

Page 35: ...LL 560pF CAP INSTALL C341 C342 C343 WITH 120pF CAP STEP 1 STEP 2 STEP 3 STEP 4 STEP 5 REQUIRED CHANGES DENC_GND DENC_GND DENC_GND DENC_GND DENC_GND DENC_GND DENC_GND DENC_GND DENC_GND DENC_GND DENC_GND SAA7105H U24 45 42 41 RED_CR_C_CVBS GREEN_VBS_CVBS BLUE_CB_CVBS STANDARD DEFINITION AFTER MODIFICATIONS GREEN RED BLUE BLUE RED GREEN J4 RCA JACK 1 2 C343 NO POP L10 1uH C133 100pF C220 100pF R184 8...

Page 36: ...Spectrum Digital Inc 2 18 TMS320DM642 EVM Technical Reference ...

Page 37: ...3 8 3 2 9 J9 Expansion Connector 3 9 3 2 10 J10 5 Volt Input Connector 3 9 3 2 11 J11 J12 RS 232 Connectors 3 10 3 2 12 J13 Microphone Audio Input Connector 3 11 3 2 13 J14 Audio Line Output Connector 3 12 3 2 14 J15 Capture Port 1 Video Input Connector 3 12 3 2 15 J16 Capture Port 1 S Video Input Connector 3 13 3 2 16 J17 Capture Port 1 Composite Video Input Connector 3 13 3 2 17 J18 Capture Port...

Page 38: ...Spectrum Digital Inc 3 2 TMS320DM642 EVM Technical Reference Topic Page 3 3 User LEDs 3 20 3 4 System Status LEDs 3 20 3 5 Reset Switch S3 3 21 3 6 Test Points 3 21 ...

Page 39: ...inch 210 x 115 mm multi layer board which is powered by an external 5 volt only power supply Figure 3 1 shows the layout of the DM642 EVM Figure 3 1 TMS320DM642 EVM S3 J5 J7 P2 J8 J9 J12 J4 J3 J2 J1 J11 J13 J10 J6 DC_P1 DS1 DS9 DC_P2 DC_P3 J17 J15 J16 J18 J19 Bottom J14 JP1 ...

Page 40: ...ideo Out Blue J5 15 VGA Video Out J6 6 FPGA Optional JTAG Programmer Header J7 14 JTAG J8 8 Ethernet J9 3 SPDIF J10 2 5 Volts In J11 9 RS 232 J12 10 RS 232 J13 2 Microphone Audio Line In J14 2 Audio Line Out J15 2 Composite Video In J16 4 S Video In J17 2 Composite Video In J18 2 Composite Video In J19 60 60 Pin Emulation header bottom side JP1 2 Optional Reset Header P2 124 PCI Bus Connector DC_P...

Page 41: ...own below 3 2 2 J2 Video Out RED and Pr J2 is a RCA jack which drives the RED signal when the encoder is in the R G B mode This output is also used in HDTV mode to drive the Pr component of the video The pinout of this connector is shown below Table 2 J1 Mini Din Connector Pin Signal Name 1 Ground 2 Ground 3 Luma Y 4 Chroma C Pin 1 Pin 2 Pin 3 Pin 4 Figure 3 2 Front View Mini Din Connector Figure ...

Page 42: ... HDTV mode to drive the Y component of the video The pinout of this connector is shown below 3 2 4 J4 Video Out Blue and Pb J4 is an RCA jack used to interface to the Blue of an RGB device This connector is driven directly by the Philips SAA7105 video encoder This output is also used in HDTV mode to drive the Pb component of the video The pinout of this connector is shown below Figure 3 4 J3 RCA J...

Page 43: ...ouble row header allowing JTAG programming the FPGA U8 The signals on the pins are shown in the table below This interfaces to a Xilinx programming pod Table 3 J5 PC Video Output Connector Pin Signal Name 1 Red 2 Green 3 Blue 4 No connect 5 Ground 6 Ground 7 Ground 8 Ground 9 Key 10 Ground 11 No connect 12 No connect 13 Horizontal Sync 14 Vertical sync 15 No Connect Table 4 J6 FPGA Programming Con...

Page 44: ...ow 3 2 8 J8 Ethernet Connector Connector J8 is a standard RJ 45 ethernet connector The connector pin out is shown Table 5 J8 Connector Pin Out Pin Signal Name 1 LXT TXD 2 LXT TXM 3 LXT RXP 4 Terminator 1 5 Terminator 2 6 LXT RXM 7 Terminator 3 8 Terminator 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 TMS TDI PD 3 3V TDO TCK RET TCK EMU0 TRST GND no pin key GND GND GND EMU1 Header Dimensions Pin to Pin spaci...

Page 45: ...elow 3 2 10 J10 5 Volt Input Connector The DM642 EVM can be powered either standalone or from the PCI bus The input supply is 5 volts only In the standalone mode power 5 volts is brought onto the TMS320DM642 EVM via connector J10 The connector has an outside diameter of 5 5 mm and an inside diameter of 2 5 mm The A diagram of J10 is shown below Figure 3 7 J9 RCA Jack Shield ground Signal Output PC...

Page 46: ... shown below The pin numbers and their corresponding signals are shown in the table below This corresponds to a standard dual row to DB 9 connector interface used on personal computers The pin numbers for J12 and their corresponding signals are shown in the table below Table 6 J11 RS 232 Pinout Pin Signal Name Direction 1 DCD In 2 RXD In 3 TXD Out 4 DTR Out 5 GND N A 6 DSR In 7 RTS Out 8 CTS In 9 ...

Page 47: ...are connected to the microphone so it is monaural The signals on the plug are shown in the figure below The audio line in is a stereo input The input connector is a 3 5 mm stereo jack located at the bottom position of J13 The signals on the mating plug are shown in the figure below Microphone In Ground Figure 3 10 Microphone Stereo Jack Microphone Bias Left Line In Ground Figure 3 11 Audio Line In...

Page 48: ...e mating plug are shown in the figure below 3 2 14 J15 Capture Port 1 Video Input Connector J15 is an RCA jack used to capture composite video for capture channel 1 This connector is driven directly into the TI TVP5146 video decoder The pinout of this connector is shown below Left Line Out Ground Figure 3 12 Audio Line Out Stereo Jack Right Line Out Figure 3 13 J15 RCA Jack Shield ground Signal In...

Page 49: ...ector is shown below 3 2 16 J17 Capture Port 2 Video Input Connector J17 is an RCA jack used to interface composite video source to capture channel 2 This connector is driven directly into the TI TVP5150A video decoder The pinout of this connector is shown below Table 8 J1 Mini Din Connector Pin Signal Name 1 Ground 2 Ground 3 Luma Y 4 Chroma C Pin 1 Pin 2 Pin 3 Pin 4 Figure 3 14 Front View Mini D...

Page 50: ...tion capability The signals on this connector are 4 columns by 15 rows as shown in the table below Table 9 J19 60 Pin Emulation Connector Row Column A Signal Name Column B Signal Name Column C Signal Name Column D Signal Name 1 Ground IDO ID2 Ground 2 Ground TMS EMU18 Ground 3 Ground EMU17 TRSTn Ground 4 Ground TDI EMU16 Ground 5 Ground EMU14 EMU15 Ground 6 Ground EMU12 EMU13 Ground 7 Ground TDO E...

Page 51: ...21 3 3 Volts Not Used 22 AD28 I O Z Address Data 28 23 AD26 I O Z Address Data 26 24 GND 25 AD24 I O Z Address Data 24 26 IDSEL I Initialization Device Select 27 3 3 Volts Not Used 28 AD22 I O Z Address Data 22 29 AD20 I O Z Address Data 20 30 GND Ground 31 AD18 I O Z Address Data 18 32 AD16 I O Z Address Data 16 33 3 3 Volts Not Used 34 FRAME I Frame 35 GND Ground 36 TRDY I O Z Target Ready 37 GN...

Page 52: ...ed 26 C BE3 I O Z Command Byte Enable 3 27 AD23 I O Z Address Data 23 28 GND Ground 29 AD21 I O Z Address Data 21 30 AD19 I O Z Address Data 19 31 3 3 Volts Not Used 32 AD17 I O Z Address Data 17 33 C BE2 I O Z Command Byte Enable 2 34 GND Ground 35 IRDY I Initiator Ready 36 3 3 Volts Not Used 37 DEVSEL I O Z Device Select 38 GND Ground 39 LOCK I Resource Locked 40 PERR I O Z Parity Error 41 3 3 V...

Page 53: ... 2 D4 38 VP2D5 I O Z Video Port 2 D5 39 GND System Ground 40 GND System Ground 41 VP2D2 I O Z Video Port 2 D2 42 VP2D3 I O Z Video Port 2 D3 43 VP2D0 I O Z Video Port 2 D0 44 VP2D1 I O Z Video Port 2 D1 45 GND System Ground 46 GND System Ground 47 VP2CLK0 I O Z Video Port 2 Clock 0 48 GND System Ground 49 GND System Ground 50 GND System Ground 51 VP2CTL0 I O Z Video Port 2 Control 0 52 VP2CTL1 I O...

Page 54: ... 37 GND System Ground 38 VP0CTL0 I O Z Video Port 0 Control 0 39 VP0CTL1 I O Z Video Port 0 Control 1 40 GND System Ground 41 GND System Ground 42 GND System Ground 43 GND System Ground 44 VP0CLK1 I O Z Video Port 0 Clock 1 45 VP0CLK0 I O Z Video Port 0 Clock 0 46 GND System Ground 47 GND System Ground 48 GND System Ground 49 GND System Ground 50 VP1CLK1 I O Z Video Port 1 Clock 1 51 VP1CLK0 I O Z...

Page 55: ... EMIF Data D3 38 DC_D2 I O Z EMIF Data D2 39 DC_D1 I O Z EMIF Data D1 40 DC_D0 I O Z EMIF Data D0 41 GND System Ground 42 GND System Ground 43 Reserved 44 DC_ECLKOUT2 O EMIF CLKOUT2 45 GND System Ground 46 GND System Ground 47 DC_BE3 O EMIF Byte Strobe 48 DC_BE2 O EMIF Byte Strobe2 49 DC_BE1 O EMIF Byte Strobe1 50 DC_BE0 O EMIF Byte Strobe0 51 GND System Ground 52 GND System Ground 53 DC_CE3 O EMI...

Page 56: ... the table below Table 15 DM642 LEDS LED Number Color Function DS1 Green Programmable via FPGA LED Register D0 DS2 Green Programmable via FPGA LED Register D1 DS3 Green Programmable via FPGA LED Register D2 DS4 Green Programmable via FPGA LED Register D3 DS5 Green Programmable via FPGA LED Register D4 DS6 Green Programmable via FPGA LED Register D5 DS7 Green Programmable via FPGA LED Register D6 D...

Page 57: ... button Reset switch S3 When this button is pressed the EVM is put through the reset state There is also an optional 2 pin Reset header JP1 which is connected in parallel to the Reset switch S3 When this header is shorted the EVM is put into reset 3 6 Test Points TheTMS320DM642 EVM has 23 test points Their position are shown in the figure below Figure 3 17 TMS320DM642 EVM Test Points TP6 TP5 TP3 T...

Page 58: ...P5 GND Ground TP6 GND Ground TP7 TDPT DM642 DPT Pin TP8 VCC3 3 I O Main 3 3 Volt Power TP9 PWR OK I O Core Power In Range TP10 GND Ground TP11 GND Ground TP12 MDINT_TP PHY Status Interrupt TP13 1 8 Volts FPGA Core power TP14 RESET System Reset TP15 OUT3 Encoder 3 3 Volts TP16 1 8V DEC Decoder 1 8 Volts TP17 VICTP VIC IF Test Point TP18 VDAC DM642 VDAC Output Pin TP19 STCLK VIC STCLK Input TP20 CLK...

Page 59: ...A 1 Appendix A Schematics This appendix contains the schematics for the TMS320DM642 EVM ...

Page 60: ...ins 9 SDRAM 10 Expansion EMIF Buffers 11 Flash and Dual UART 12 RS232 Buffers 13 Video Port Expansion Switches 14 Video Port Daugher Card Connector 15 EMIF Daughter Card Connector 16 OSD FPGA 17 OSD FPGA Power 18 Video Decoder 1 19 Video Decoder 2 20 Video Encoder 21 Ethernet 22 PCI 23 AIC23 Audio Interface 24 Power 25 FPGA Power Reset Circuitry REV ENGR 2 REVISION STATUS OF SHEETS 1 11 SH DATE 14...

Page 61: ...with TI Decoders Version 3 SPECTRUM DIGITAL INCORPORATED B 2 25 Wednesday October 13 2004 Title Size Document Number Rev Date Sheet of GND USER_LED0 16 USER_LED1 16 USER_LED2 16 USER_LED3 16 USER_LED4 16 USER_LED5 16 USER_LED6 16 USER_LED7 16 BOOT_MODE1 4 10 BOOT_MODE0 4 10 LENDIAN_MODE 3 14 PCI_EEAI 3 14 EMIF_ECLKINSEL0 4 10 EMIF_ECLKINSEL1 4 10 SPDIF_OUT 6 EXP_AUDIO_EN 6 14 VCC3 3 GND VCC3 3 VCC...

Page 62: ...PGA_LOCK 17 SYSTEM_RESET 11 14 16 17 18 19 20 21 25 EMULATOR_RSTn 5 VCC3 3 VCC3 3 VCC3 3 VCC3 3 VCC3 3 VCC3 3 VCC3 3 VCC3 3 VCC3 3 VCC3 3 VCC3 3 VCC3 3 VCC3 3 C39 0 1uF C40 10uF E1 EXCCET103U EMI FILTER 1 3 2 I O GND TP21 TP 1 TP20 TP 1 R66 2K R67 2K R174 NO POP R205 NO POP R203 10K R173 360 R217 10K R171 NO POP C119 0 1uF RN27 RPACK4 10K 1 2 3 4 5 6 7 8 C364 0 1uF R101 2K C190 0 1uF R172 1K C188 ...

Page 63: ...P_TCLK 5 DSP_TDI 5 DSP_TRST 5 DSP_TDO 5 DSP_TMS 5 DSP_EMU5 5 DSP_EMU8 5 DSP_EMU4 5 DSP_EMU9 5 DSP_EMU6 5 DSP_EMU7 5 DSP_EMU11 5 DSP_EMU10 5 BOOT_MODE1 2 10 BOOT_MODE0 2 10 EMIF_ECLKINSEL0 2 10 EMIF_ECLKINSEL1 2 10 VCC3 3 GND TSDWE 9 10 TAOE 9 10 TSDCAS 9 10 TAWE 9 10 TSDRAS 9 10 TARE 9 10 VCC3 3 VCC3 3 RN5 RPACK8 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 R97 33 RN17 RPACK8 33 1 2 3 4 5 6 7 8 9 10 ...

Page 64: ...DSP_EMU11 4 DSP_TCLK 4 DSP_TRST 4 GND VCC3 3 EMULATOR_RSTn 3 VCC3 3 VCC3 3 VCC3 3 VCC3 3 VCC3 3 VCC3 3 VCC3 3 VCC3 3 VCC3 3 VCC3 3 R272 10K R183 1K R244 NO POP U31 SN74LVC1G32 1 2 4 5 3 RN3D 39 RN4C 39 RN3E 39 RN4D 39 R180 33 R178 33 U30 SN74LVC1G32 1 2 4 5 3 RN4A 39 RN4B 39 R179 100 1 C279 0 1uF J7 HEADER 7x2 Emulation 1 3 5 7 9 2 4 8 10 11 12 13 14 C280 18pF J19 HEADER 4x15 A1 A2 A3 A4 A5 A6 A7 ...

Page 65: ...1 AB11 AB12 AF14 AF12 AE17 AC17 AD17 AF8 AF10 AF4 AE5 AD5 C8 D8 A9 B9 C9 D9 A10 B10 C10 D10 A11 B11 C11 D11 E11 B12 C12 D12 E12 E13 A7 A13 B8 D7 C7 AD1 AC1 VP0_D00 VP0_D01 CLKX0 VP0_D02 FSX0 VP0_D03 DX0 VP0_D04 CLKS0 VP0_D05 DR0 VP0_D06 FSR0 VP0_D07 CLKR0 VP0_D08 VP0_D09 VP0_D10 VP0_D11 ACLKR0 VP0_D12 AFSR0 VP0_D13 AHCLKR0 VP0_D14 AMUTEIN VP0_D15 AMUTE VP0_D16 ACLKX0 VP0_D17 AFSX0 VP0_D18 AHCLKX0 ...

Page 66: ...0 21 MTXEN 21 EMAC_ENABLE 3 14 VCC3 3 VCC5 VCC3 3 VCC5 VCC3 3 VCC3 3 VCC3 3 VCC3 3 U51 SN74CBT16233DGGR 56 1 30 14 13 44 27 2 53 5 50 8 47 11 55 3 52 6 49 9 46 12 54 4 51 7 48 10 45 29 28 42 16 39 19 36 22 33 25 41 17 38 20 35 23 32 26 15 40 18 37 21 34 24 31 43 1B1 1A SEL1 VCC DGND DGND TEST1 2B1 3B1 4B1 5B1 6B1 7B1 8B1 1B2 2B2 3B2 4B2 5B2 6B2 7B2 8B2 2A 3A 4A 5A 6A 7A 8A SEL2 TEST2 9B1 10B1 11B1...

Page 67: ... Y15 Y18 AB4 AA4 AA5 AA8 AA10 AA11 AA13 AA14 AA16 AA17 AA19 AA22 AB1 AB2 AB6 AB9 AB18 AB21 AB26 AC3 AC5 AC18 AC22 AC24 AD2 B2 B25 C3 C24 D4 D23 E5 E22 G14 J6 N20 P7 W25 Y13 AB5 AB22 AC23 AD24 AE2 AE25 M12 M13 M14 M15 N12 N13 N14 N15 P12 P13 P14 P15 R12 R13 R14 R15 H21 H26 J5 J7 J20 J22 K6 K21 L1 L6 L21 M7 M20 N5 N6 N21 N25 AD4 AD18 AE3 AE8 AE10 AE12 AE14 AE19 AE24 AF1 AF7 AF9 AF11 AF13 AF15 AF19 A...

Page 68: ...48LC4M32B2 2 4 5 7 8 10 11 13 22 23 24 25 26 27 45 47 48 50 51 53 54 56 68 77 60 61 62 63 64 65 66 74 76 79 80 82 83 85 31 33 34 36 37 39 40 42 44 58 72 86 12 6 32 38 46 52 78 84 1 15 29 43 3 9 35 41 49 55 75 81 18 67 19 17 20 16 71 28 59 21 14 30 57 69 70 73 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 BA0 BA1 A10 A0 A1 A2 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CLK DQ10 A3 A4 A5 A6 A7 A8 A9 DQ8 DQ9 DQ11 DQ12...

Page 69: ...16245B 7 18 31 42 47 46 44 43 41 40 38 37 2 3 5 6 8 9 11 12 36 35 33 32 30 29 27 26 13 14 16 17 19 20 22 23 48 1 25 24 4 10 15 21 28 34 39 45 Vcc Vcc Vcc Vcc 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 1OE 1DIR 2OE 2DIR GND GND GND GND GND GND GND GND U4 SN74LVT16245B 7 18 31 42 47 46 44 43 41 40 38 37 2 3 5 6 8 9 ...

Page 70: ...A_DSR 12 UART_A_CTS 12 DC_AWE 10 15 16 DC_ARE 10 15 16 DC_EMIFA_OE 10 DC_EMIFA_DIR 10 VCC3 3 GND FPGA_DC_EMIF_DIR 16 FPGA_DC_EMIF_OE 16 TCE2 4 10 TCE3 4 10 TSOE3 4 16 FLASH_EXT_A22 16 VCC3 3 VCC3 3 VCC3 3 VCC3 3 VCC3 3 VCC3 3 VCC3 3 VCC3 3 VCC3 3 C71 NO POP C73 0 1uF C72 001uF L1 BLM21P221SN R36 33 U9 TL16C752B 44 45 46 47 48 1 2 3 28 27 26 24 10 11 36 9 19 15 4 5 7 40 8 16 23 20 38 39 21 12 13 14...

Page 71: ...B_DTR UART_B_DSR 11 UART_B_DCD 11 UART_B_DTR 11 UART_B_CTS 11 UART_B_RI 11 UART_B_RTS 11 UART_B_RX 11 S_B_RTS S_B_RXD S_B_CTS S_B_RI S_B_DCD S_B_DTR S_B_DSR S_B_TXD GND VCC3 3 UART_B_TX 11 VCC3 3 VCC3 3 VCC3 3 VCC3 3 VCC3 3 C6 47uF C53 0 1uF J12 HEADER 5X2 1 2 3 4 5 6 7 8 9 10 J11 DB9 MALE 5 9 4 8 3 7 2 6 1 R7 10 R6 10K C52 1uF C50 1uF C51 1uF C66 1uF C68 1uF R34 10K R35 10 C70 0 1uF C9 47uF C67 1...

Page 72: ...LK1 6 14 VP2CTL0 6 14 VP2CTL1 6 14 4 1V SW_VP2CTL2 16 SW_VP2CLK0 16 SW_VP2CLK1 16 SW_VP2CTL0 16 SW_VP2CTL1 16 IXCLK_A 18 IXCLK_B 19 GND VCC5 B_INData 0 7 19 VP1D 0 19 6 14 EXP_DISPLAY_EN 14 EXP_CAPTURE1_EN 14 EXP_CAPTURE2_EN 14 FID_CTL2_B 19 FID_CTL2_A 18 A_INData 0 9 18 VCC5 4 1V 4 1V 4 1V VCC5 4 1V 4 1V 4 1V U48 SN74CBTS3384 1 13 3 4 7 8 11 2 5 6 9 10 14 17 18 21 22 24 12 15 16 19 20 23 1OE 2OE ...

Page 73: ...7 16 DCARD_STCLK 6 DSP_SDA0 3 18 19 20 23 USER_GPIO_3 16 VP2CTL1 6 13 VCC3 3 GND VP2D 0 19 6 13 VCC5 VP1CLK1 6 VP0CTL2 6 13 EXP_AUDIO_EN 2 6 VP1CLK0 6 13 VP0CLK0 6 13 VP0CTL1 6 13 VP1CTL2 6 13 VCC5 VCC3 3 VCC5 VCC3 3 VCC3 3 VCC5 DC_P2 CONNECTOR 45 X 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 5...

Page 74: ..._A5 DC_A18 DC_A11 DC_A16 DC_A17 DC_A12 DC_A13 DC_A4 GND DC_A 22 3 10 11 16 DC_D 31 0 10 11 16 DC_BE2 10 DC_BE3 10 DC_BE0 10 DC_BE1 10 DC_ECLKOUT2 10 16 DC_CE2 10 16 DC_CE3 10 16 DC_AOE 10 11 16 DC_ARE 10 11 16 DC_AWE 10 11 16 DC_ARDY 10 VCC3 3 GND VCC3 3 VCC3 3 R241 4 7K DC_P3 CONNECTOR 45 X 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 ...

Page 75: ..._HSYNC 20 FPGA_DIN 3 DENCDATA 0 11 20 VCC3 3 VCC3 3 VCC3 3 RN30 RPACK8 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 U8A XC2S300E 7TQ208C 160 161 162 163 164 165 166 167 192 193 194 198 199 200 201 202 203 204 205 206 11 153 154 169 173 174 175 176 178 179 180 181 182 168 152 151 150 149 148 147 146 145 141 140 139 73 71 70 69 68 64 63 62 61 60 59 58 57 56 55 24 23 22 21 20 18 17 16 15 10 9 8 7 6 5 4 ...

Page 76: ...208 2 157 159 207 54 50 52 104 106 155 14 28 37 67 76 90 119 195 196 184 177 171 156 186 172 142 128 197 190 183 170 158 144 137 131 124 117 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 VCC01 VCC02 VCC03 VCC04 VCC05 VCC06 VCC07 VCC08 VCC09 VCC10 VCC11 VCC16 TMS TDO TDI TCK M2 M1 M0 DONE PROG CCLK VCCINT1 VCCINT2 VCCINT3 VCCINT4 VCCINT5 VCCINT6 VCCINT7 VCCINT12 VCC15 VCC14 G...

Page 77: ...R111 2 2K TP26 TestPoint 1 R79 4 7K TP25 TestPoint 1 TP24 TestPoint 1 C366 680pF C140 0 1uF Y1 14 31818mhz J16 750317 2 3 4 2 1 5 6 C166 330pF R239 0 R82 22 RN19 RPACK8 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 C135 330pF C231 0 1uF C141 0 1uF C230 0 1uF J15 RCA JACK YELLOW 1 2 R104 75 0 C223 680pF C175 1uF C172 0 1uF C165 1uF C178 0 1uF C170 0 1uF C176 0 1uF C179 0 1uF C143 0 1uF C138 0 1uF C142 ...

Page 78: ...DDEC 1 8VA_DDEC 3 3VD_DDEC 1 8VD_DDEC 1 8VD_DDEC 3 3VD_DDEC 1 8VD_DDEC 3 3VD_DDEC 1 8VA_DDEC 3 3VD_DDEC 3 3VD_DDEC VCC3 3 3 3VD_DDEC 3 3VA_DDEC 3 3VD_DDEC VCC3 3 TP16 TestPoint 1 TP29 TestPoint 1 C292 680pF L49 2 7uH L50 2 7uH R259 75 C290 330pF R258 0 C227 1uF C300 330pF C357 22uF U29 TPS73618DCQ 3 5 1 2 6 4 GND EN IN1 OUT1 TAB GND NR FB C45 22uF C228 680pF R142 NO POP C294 680pF R189 100K R140 2...

Page 79: ... 3 OUT_3 3V VCC5 VCC3 3 VCC5 J2 RCA JACK 1 2 J3 RCA JACK 1 2 C328 33pF C326 33pF C46 10uF C338 0 1uF C324 0 1uF C47 10uF U38 TPS76833QPWP 3 5 6 7 13 14 16 1 2 9 10 11 12 20 19 4 8 18 17 15 21 GND ENn IN1 IN2 OUT2 OUT1 RESET PG HS GND1 HS GND2 HS GND3 HS GND4 HS GND5 HS GND6 HS GND8 HS GND7 NC1 NC2 NC4 NC3 FB PWRPAD Y3 27 000Mhz C216 0 1uF C215 0 1uF L31 NO POP 10uH R103 82 C281 0 1uF C217 0 1uF C3...

Page 80: ...C3 3 AVCC3 3 VCC3 3 VCC3 3 VCC3 3 VCC3 3 U44 25 MHz 4 3 2 1 VCC OUT GND EN R195 49 9 R157 49 9 R200 NO POP R230 NO POP U45 LXT971ALC 55 57 58 59 60 56 54 62 63 52 48 47 46 45 49 53 3 43 42 64 27 28 19 20 23 24 38 37 36 12 13 14 15 16 2 1 39 17 35 4 34 22 25 26 7 11 18 41 50 61 51 8 40 21 29 30 31 5 6 33 32 9 10 44 TX_CLK TXD0 TXD1 TXD2 TXD3 TX_EN TX_ER COL CRS RX_CLK RXD0 RXD1 RXD2 RXD3 RX_DV RX_E...

Page 81: ...7 PCI_PERRz 7 PCI_IDSEL 7 PCI_CBEz3 7 PCI_CLK 7 PCI_GNTz 7 PCI_REQz 7 PCI4 1V 7 VCC3 3 VCC5 PCIVCC3 3 PCIVCC3 3 VCC5 VCC5 VCC3 3 VCC5 VCC3 3 VCC5 R233 0 U40 74CBT3245A 2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 19 1 20 10 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 G NC VCC GND U43 CBTD16210DGGR_3 47 48 2 13 46 35 8 17 32 41 15 3 4 5 6 7 9 10 11 12 14 16 18 19 20 21 22 23 24 1 45 44 43 42 40 39 3...

Page 82: ...SN R27 4 7K R28 4 7K R56 33 C110 470nF R51 0 C62 33pF C64 1uF C105 NO POP C102 NO POP J14 Line Out 3 4 2 1 C21 10uF C108 470nF C63 NO POP C109 470nF C111 470nF C107 0 1uF C58 NO POP C12 10uF C59 NO POP R53 47K R54 47K R75 100 R26 0 L4 BLM21P221SN R33 2 2 L8 BLM21P221SN RN9 RPACK4 33 1 2 3 4 5 6 7 8 R52 100 PW Package U19 TLV320AIC23 22 14 11 15 25 3 4 5 21 24 23 10 9 28 16 17 18 20 19 26 13 12 8 1...

Page 83: ...8 VCC3 3 GND VCC5 AGND DSP_CVDD VCC3 3 VCC5 VCC3 3 VCC5 VCC3 3 VCC3 3 AGND VCC5 C5 10uF C37 10uF TP1 TP 1 TP11 TP 1 TP10 TP 1 TP5 TP 1 TP3 TP 1 TP6 TP 1 C148 1000pF U22 TPS54310PWP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 AGND VSENSE COMP PWRGD BOOT PH1 PH2 PH3 PH4 PH5 PGND1 PGND2 PGND3 VIN1 VIN2 VIN3 VBIAS SS ENA SYNC RT POWERPAD C116 0 1uF L11 2 7 uH C16 0 047uF C15 560pF U17 TPS543...

Page 84: ...1 8V FPGA1 8V 4 1V 4 1V VCC3 3 VCC5 VCC3 3 VCC3 3 VCC3 3 VCC5 VCC3 3 VCC3 3 VCC5 R147 360 100687 3601 R148 10K C240 1uF R155 33 R152 10K R113 1 6K DS11 YELLOW TP14 TP 1 R151 NO POP R150 NO POP R153 10K R154 10K U33 TPS3307 18D 8 7 1 2 3 4 6 5 VDD MR SENSE1 SENSE2 SENSE3 GND RESET RESET C239 0 1uF S3 PUSHBUTTON SW D6 LM4040DCIM3 4 1 2 1 U1 TPS76701QPWP 3 5 6 7 13 14 16 1 2 9 10 11 12 20 19 4 8 18 1...

Page 85: ...B 1 Appendix B Mechanical Information This appendix contains the mechanical information about the TMS320DM642 EVM produced by Spectrum Digital ...

Page 86: ...Spectrum Digital Inc B 2 TMS320DM642 EVM Technical Reference THIS DRAWING IS NOT TO SCALE ...

Page 87: ......

Page 88: ...Printed in U S A December 2004 507345 0001 Rev B ...

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