Spectrum Digital TMS320DM642, Technical Reference

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Spectrum Digital, Inc
2-6 TMS320DM642 EVM Technical Reference
2.1.5 FPGA Synchronous Memory Interface
The FPGA implements synchronous registers in the CE3 space. These registers are
used primarily for on screen display functions and some EVM glue functions. A list of
the synchronous registers is shown in the table below.
2.1.6 EMIF Buffer/Decoder Control
The EMIF buffer and decode functions are implemented with a GAL16LV8D generic
array logic device, U15. the device performs basic decode for the flash and UART
along with buffer control for CE1, CE2, and CE3. The VHDL is shown below.
FLASH_CE <= ‘0’ when A22 =’0’ and CE1 = ‘0’ else ‘1’;
UART_CSA <= ‘0’ when A22 = ‘1’ and A8 = ‘0’ and A7 = ‘0’
and A6 = ‘0’ and CE1 = ‘0’ else ‘1’;
UART_CSB <= ‘0’ when A22 = ‘1’ and A8 = ‘0’ and A7 = ‘0’
and A6 = ‘1’ and CE1 = ‘0’ else ‘1’;
EMIF_OE <= ‘0’ when CE1 = ‘0’ or CE2 =’0’ or CE3 = 0’ else ‘1’;
EMIF_DIR <= ‘1’ when (CE1 = ‘0’ and AOE =’0’) or
(CE2 = ‘0’ and AOE =’0’) or
(CE3 = ‘0’ and AOE =’0’) else ‘0’;
Table 7: FPGA Synchronous Memory Interface
Address Function R/W Bits
0xB000 0000 Synchronous Test Register R/W 32
0xB000 0004 Audio PLL Data Register R/W 16
0xB000 0008 OSD XSTART R/W 12
0xB000 000C OSD YSTART R/W 12
0xB000 0010 OSD XSTOP R/W 12
0xB000 0014 OSD YSTOP R/W 12
0xB000 0018 Events Per Field R/W 16
0xB000 001C
0xB000 003C
Reserved R 32
0xB000 0040 OSD Data FIFO W 32
0xB000 0044 OSD CLUT W 32
0xB000 0048
0xB000 007C
Reserved R 32