Spectrum Digital TMS320DM642, Technical Reference

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Spectrum Digital, Inc
1-5
1.4 Memory Map
The C64xx family of DSPs has a large byte addressable address space. Program code
and data can be placed anywhere in the unified address space. Addresses are always
32-bits wide.
The memory map shows the address space of a generic DM642 processor on the left
with specific details of how each region is used on the right. By default, the internal
memory sits at the beginning of the address space. Portions of memory can be
remapped in software as L2 cache rather than fixed RAM.
The EMIF (External Memory Interface) has 4 separate addressable regions called
chip enable spaces (CE0-CE3). The SDRAM occupies CE0 while the Flash, UART,
and FPGA are mapped to CE1. Daughter cards use CE2 and CE3. CE3 is configured
for synchronous operation for on screen display functions and other synchronous
registers implemented in the external FPGA.
Internal Memory/Cache
DM642 EVM
Reserved
or
Peripheral
SDRAM
Flash
UART/FPGA Regs
Daughter
Card
FPGA Sync Regs
Daughter Card
Generic DM642
Address Space Address
0x00000000
0x00040000
0x80000000
0x90000000
0xA0000000
0xB0000000
Internal Memory/Cache
EMIF CE0
EMIF CE1
EMIF CE2
EMIF CE3
Reserved Space
or
Peripheral Registers
Figure 1-2, Memory Map, DM642 EVM