Sony MDDISCAM DCM-M1, Service Manual

Page: 59 / 198

DCM-M1
MAIN BOARD (5/7)
(SEE PAGE 4-48, 59)
CLE
UDQM
X8001
32kHz
RFAL TIME CLOCK
IC8008
SYSTEM CONTROL
IC8001
CLOCK_EN
OSC OUT
OSC IN
DQMUU_ICIOWR
RD/WT
DQMUL_ICIORD
3
2
4
7
8
9
92
93
2
ALE
3
43
41
15
UDQM
39
/WE
16
/CE
19
/CAS
17
/RAS
18
CKE
37
CLK
38
VOUT 3
VCC 4
91
CN8101
(2/3)
21
20
24
22
29
23
DATA_TO_HI
XHI_SCK
DATA_FROM_HI
CAM_XCS
CAM_RST
CAM_DD_ON
LCD_SI
LCD_SCK
LCD_SO
LCD_EN_SWED
IC8007
IC8025
IC8006
TO CAMERA CONTROL
(SEE PAGE 3-6)
TO AUDIO
(SEE PAGE 3-17)
167 CAM ENABLE
186 CAM PWR
184 CAM RESET
171
182
LCD_EN 103
EVF_EN 107
165
164
189
SO
SCLK
SI
CE
190
CAM_SI
CAM_SCK
CAM_SO
ATRAC2_EN
ADA_EN
CAM_SI
CAM_SCK
CAM_SO
ATRAC2_EN
ADA_EN
DRV_REQ
169 DRV_REQ
155 XTAL
156 EXTAL
XTAL2
EXTAL2
168
170
174
176
RATE_TX
RATE_RTS
RATE_RX
RATE_CTS
DEV_RESET
RATE_TX
RATE_RTS
RATE_RX
RATE_CTS
177 DEV_RESET
193 XRESET
185 DRV_PWR
X8002
32KHz
4
5
X8003
9.8304MHz
SWITCH
Q8005
SWITCH
Q8013
SWITCH
Q8014
RESET
IC8009
IC8010
SH_3.1V
IC8023
6
4
2 2
4
1
1
2
IC8013
05
CN4312
(1/2)
3
14
2
1
TO LCD
(SEE PAGE 3-19)
IC4007
2 6
1
IC4008
2 6
1
IC4008
5 3
7
IC4007
5 3
7
EVF_SI
EVF_SCK
EVF_SO
EVF_EN_SWED
CN4511
(2/2)
CN4313 (3/3)
9
10
8
7
IC4010
2 6
1
IC4011
2 6
1
IC4011
5 3
7
IC4010
5 3
7
ETHER_PWR
SBHE_CE2B
CN8007
(2/3)
36
27
ETHER_INT
33
CS6_ETHER
ETHER_WAIT
SYS_WAIT
SYSCHIP_INT
FSY_INT
CPU_CS4_100
DEV_RESET
A0 – A3
D0 – D15
DQMUL_ICIORD
DQMUU_ICIOWR
RD & WT
DQMUL_ICIORD
DQMUU_ICIOWR
DQMLL_WE0
DQMLU_WE1
RD
26
DQMLU_WE1
CS3_SDRAM
DQMLL_WE0
90
99
98
96
89
ETHER_PWR 94
ETHER_INT 138
SBHE_CE2B 104
CS6_ETHER 102
13 – 18
•
20
•
22 – 26
•
28
•
30 – 32
•
34
•
36 – 44
•
46
•
48 – 52
53 – 56
•
58
•
60 – 68
•
70
•
72 – 78
•
80
•
82
20 – 26
•
29 – 35
2
•
4
•
5
•
7
•
8
•
10
•
11
•
13
•
42
•
44
•
45
•
47
•
48
•
50
•
51
•
53
A0 ı
A13
DQ0
ı
DQ15
UDQM
15
UDQM
39
/WE
16
/CE
19
/CAS
17
/RAS
18
CKE
37
CLK
38
20 – 26
•
29 – 35
2
•
4
•
5
•
7
•
8
•
10
•
11
•
13
•
42
•
44
•
45
•
47
•
48
•
50
•
51
•
53
A0 ı
A13
DQ0
ı
DQ15
CAS 108
RAS3L 106
CKE 105
KIO 162
123
137
139
100
WAIT
CS2_FLASH
88 RD
SYSCHIP_INT
FSY_INT
CS4_SYSCHIP
110 CLE
112 ALE
113 CE
191 RDY_BUSY
CSO_ROM
2
1
4
2
1
4
1
2
4
28
29
34
31
A2
–
A13,
A22, A23 A2
–
A13,
A22, A23
D16
–
D31
D0
–
D15
64M SDRAM
IC8002
64M SDRAM
IC8003
64M FLASH
IC8005
DATA BUS
ADDRESS BUS
DATA BUS
ADDRESS BUS
D0–D15
A0 – A3
D0 – D31 D0 – D7
A0 – A23
D0 – D7
A0 – A16
1
ı
4
•
6
ı
9
•
11
ı
13
•
15
ı
19
21
ı
24
42
4
5
18
ı
21
•
24
ı
27
I/O-0
ı
I/O-7
RE
WE
WP
CE
R/B
30
32
9
1M EEPROM
IC8004
21
ı
23
•
25
ı
29
I/O-0
ı
I/O-7
A0
ı
A6
A0
ı
A23
D0
ı
D31
OE
5 WE
CE
RDY/BAO
6
RES
SWITCH
Q8012
1
ı
4
•
7
•
10
ı
20
•
31
C
TO CAMERA SIGNAL PROCESS
(SEE PAGE 3-4)
B
18
TO MD SERVO
(SEE PAGE 3-14)
19
TO MPEG ENCODE
(SEE PAGE 3-10)
12
I
TO EVF
(SEE PAGE 3-21)
J
TO ETHER INTERFACE
(SEE PAGE 3-25)
K
TO A/V DATA CONTROL,
VIDEO OUT
(SEE PAGE 3-8)
8
32.768 kHz
REC/PB
408 mVp-p
9.8304 MHz
REC/PB
1.1 Vp-p
qg
32.768 kHz
REC/PB
1.5 Vp-p
qh
3-15 3-16
3-8. SYSTEM CONTROL BLOCK DIAGRAM