DCM-M1
TIMING GENERATOR
IC101
XSHD
CLPDM
XSHP
ZSG1
PBLK
AVD
ZV1
VGAT
VCK (CL)
CK
OSCO
OSCI
DSGAT
ID
SSK
AHD
SSO
SSI
SEN
RST
CAM SCK
CAM SI
CAM SO
CS CAM
CAM RST
V1
V2
V3
VSHT
V4
H1
RG
H2
CCD IMAGER
IC001
V3
V1
V2
V4
CCD OUT
RG
H2
SUB
X101
36MHz
S/H
AGC
CDS
D0
I
D9
A/D
CONVERTER
TIMING
CDS, AGC, A/D CONVERTER
IC102
PGA CONT 2
PGA CONT 1
AGC THROUGH
STBY
CAM VD
CAM FLD
CLPDM
CAMERA Y/C PROCESS
IC105 (1/2)
30
29
2
I
11
23
22 16
18 40
21
AGC CONT 1
AGC CONT 2
PBLK
19
HDO
VDO
FLDO
40
I
37
CO 0
I
CO 3
YO 0
I
YO 7
TGVD
77
TGHD
FRQ
6
OSC ADJ
IC104
ID
PBLK
ZV1
VGAT
ZSG1
TGVD
TGHD
ID
PBLK
ZV1
VGAT
ZSG1
CLPOB
78
89
I
80
AD 0
I
AD 9
BUFFER
Q001
4
3
2
1
10
H1 11
12
13
8
33
26
25
28
31
22
21
18
35
40
39
38
37
44
48
42
4
5
7
12
36
41
45
34
2
16
15
1
CLPOB
20
26
27
76
75
72
73
71
74
3
2
CHCK
69
CAMERA
Y/C
PROCESS
53
MCKO 63
VCK 65
52
51
50
I
47
45
I
42
CN101 (1/2)
29
3
7
6
8
I
15
16
I
19
Y0-Y7
C0-C3
CAM HD
CAM VD
SPCKO
CAM DD ON
VC-216 BOARD (1/2)
(SEE PAGE 4-13, 17)
2
A
1
05
TO A/V DATA CONTROL,
VIDEO OUT
(SEE PAGE 3-7)
TO SYSTEM CONTROL
(SEE PAGE 3-15)
TO CAMERA
CONTROL
(SEE PAGE 3-6)
TO CAMERA CONTROL
(SEE PAGE 3-6)
B
CHROMA
REC
Y
VIDEO SIGNAL
SIGNAL PATH
Y/CHROMA
18MHz
13.5MHz
REC/PB
H
7 Vp-p
REC/PB
2.24 Vp-p
H
REC/PB
7 Vp-p
H
36 MHz
REC/PB
1 Vp-p
18 MHz
REC/PB
3.28 Vp-p
16.33 MHz
18 MHz
REC/PB
3.12 Vp-p
REC/PB
3.84 Vp-p
H
REC/PB
3.04 Vp-p
V
REC/PB
2.88 Vp-p
2V
REC/PB
2.96 Vp-p
13.5 MHz
REC/PB
Approx.
3.4 Vp-p
H
REC/PB
3.04 Vp-p
V
REC/PB
2.88 Vp-p
3-3
3-4
3-2. CAMERA SIGNAL PROCESS BLOCK DIAGRAM
Summary of Contents for MDDISCAM DCM-M1
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