DCM-M1
MONITOR
CONTROL
CLOCK
GENERATOR
MAGNETIC
HEAD
DRIVE
SIGNAL
GENERATOR
CPU
INTERFACE
MNT0
OSCI
X5403 70.54MHz
OSCO
MNT2
SQSY
XINT
DQSY
SRDT
SWDT
SCLK
XLAT
SENS
APCREF
RECP
IC5303
FOCNT
ADFG
FS4
FS4
FILO
CLTV
PCO
FILI
ASYO
ASYO
ASYI
RFI
VC
VC
A_B
SI
SCLK SV
XLAT SV
SENS
MNT1
LRCK
DADT
XRST
FS256
XBCK
MDTI
512FS
MLRCK
MBCK
LRCK
DADT
256FS
XBCK
XINT
DQSY
SQSY
6
17
16
15
5
BUFFER
IC5302
24
10
67
55
52
51
59
58
61
60
78
13
83
25
26
27
1
2
16
17
3
8
5
6
7
9
12
11
ATRAC
ENCODER/
DECODER
HEAD
SWITCH
IC5901
OVER
WRITE
HEAD
DRIVE
Q5902,
5903
LASER
CLOCK
GENERATOR
A/D
CONVERTER
IC5102
SHOEH PROOF
MEMORY
CONTROLLER
DRAM
PLL
FILTER
COMPARATOR
14
SUBCODE
PROCESSOR
PWM
GENERATOR
SPINDLE
SERVO
ADIP
DECODER
90
79
EFM/ACIRIC
ENCODER/DECODER
MON5(HP-L)
CLK
LSRCK
MHEN
ADCCK
RECP
MON4(HP-H)
MON3(HN-L)
MON2(HN-H)
HP-L
MHEN
RFGAIN UP
RFGAIN DOWN
HP-H
HN-L
HN-H
CN5002
(1/2)
CN5803
(1/2)
CN5902
CN5901
5
6
7
8
37
12
VIN
21
89
41
HP-L
MHEN
Q5901
HP-H
HN-L
HN-H
OUT B
HR5901
OVER WRITE HEAD
OUT A
2, 3
6, 7
4, 5
8, 9
17, 18
13, 14
15, 16
11, 12
1
l
8
ADRF0
l
ADRF7
RAMADR0
l
RAMADR16
RAMDAT0
l
RAMDAT17
87
l
80
D0
l
D7
43
44
31
29
28
40
39
19
42
36
96
18
17
32 33 34
35
CLOCK
GENERATOR
SYNC
GENERATOR
SYNC
SELECTOR
SERIAL COMMAND
INTERFACE
MD1 DIGITAL SIGNAL PROCESSOR
IC5301(1/2)
MD2 DIGITAL SIGNAL PROCESSOR
IC5403(1/2)
1M FAST SRAM
IC5501
XBISY
XOE
XWE
A0
l
A16
I/O1
l
I/O8
OE
WE
DIN
REFCK
DSYNC
DDO
DCLK
X5301 22.5792MHz
OSCI
OSCO
EDEN
EDIEN
XSCSY
EDEN
EDIEN
XSCSY
TO/FROM
ADIP
D OUT
DDI
MD1X2
MD1X2
SRDTEX
XCLR
IOBUSY
XEMG
SRDT
SWDT
SCLK
XLAT
DRV
RESET
XLAT
DDX
DRV RESET
MAIN DATA SIGNAL
PROCESSING
56
–
62
•
64
–
73
1
–
4
•
13
–
21
•
29
–
32
6
•
7
•
10
•
11
•
22
•
23
•
26
•
27
46
–
50
•
53
–
55
74 75
28 12
5
CS
SRAM CS
43
44
45
46
50
43
44
45
46
50
1
2
3
4
5
CLV BOARD(1/2)
(SEE PAGE 4-75)
MAIN BOARD (3/7)
(SEE PAGE 4-39, 43)
REC BOARD
(SEE PAGE 4-79)
1
•
2
4
•
5
19
40
46
1
48
47
2
8
9
4
5
6
7
27
16
17
18
38
37
36
42
41
28
26
32
35
34
33
20
XSTBY
PIG
PIG
RFO
MOFRO
CN5001
I
24
25
3
VC
VC
VC
J
I
J
MOFRI
AGCI
RF AMP
FOCUS/TRACKING
ERROR AMP
IC5002
SWDT
COMMAND
SCLK
XLAT
DTRF
CKRF
XLRF
RF
EQ
PEAK
BOTM
EFWBL
GHWBL
SE
TE
ADFG
ABCD
FE
TEMP
AUX1
FOCNT
DPP
AD7
WRITE PWM
I GAIN
XKSHOCK
J GAIN
WBL
EQ
MODE
SERIAL
COMAND
DECODER
A/B TRACK
DETECT
IC5201, 5205(2/2)
Q5201, 5202
CENTER VOLTAGE
GENERATOR
(FOR BIAS)
AUTOMATIC
POWER CONTROL
IC5005, Q5002
RF AGC
& EQ
RF AMP
GAIN CONTROL AMP
IC5003, Q5005
L. P. F.
FL5101, Q5101
WBL
WBL
ADFM
ADIN
B.P.F.
WBL
AMP
AMP
WBL
PEAK & BOTTOM
HOLD
SLED ERROR
AMP
TRACKING
ERROR AMP
ADDER/
SUBTRACTER
AT
AMP
B.P.F
I-V
AMP
PIG
EF(XE)
HG(XF)
E&F
G&H
A
B
C
D
A
B
C
D
ABCD
AMP
PIG
IC5007
IC5008
1
7
6
5
3
5 6
2
1
7
FOCUS ERROR
AMP
BUFFER
IC5006(1/2)
COMPARATOR
IC5205(1/2)
V-I
CONVERTER
29
30
30
DETECTOR
28
21
27
23
22
26
31
SEL
XLDON
VLPC
PD-A
05
16
13
LASER
DIODE
11
13
14
G&H
E&F
I
C
D
B
A
J
LD
PD
OPTICAL PICK-UP BLOCK (1/2)
4
1
2
MD1
REC
PB
MD2
MD SIGNAL
SIGNAL PATH
MD1/MD2
100
19
TO A/V DATA CONTROL,
VIDEO OUT
(SE PAGE 3-7)
TO MD SERVO
(SE PAGE 3-14)
TO MD SERVO
(SE PAGE 3-14)
TO MD SERVO
(SE PAGE 3-14)
TO AUDIO
(SE PAGE 3-17)
TO A/V DATA
CONTROL,
VIDEO OUT
(SE PAGE 3-7)
TO MD SERVO
(SE PAGE 3-14)
200 ns
PB (MD1)
Approx.
324 mVp-p
100 ns
PB (MD2)
Approx.
360 mVp-p
200 ns
PB (MD1)
Approx.
712 mVp-p
PB (MD2)
100 ns
Approx.
280 mVp-p
200 ns
PB (MD1)
Approx.
200 mVp-p
22.5792 MHz
REC/PB
980 mVp-p
70.54 MHz
REC/PB
320 mVp-p
PB
Approx.
1.54 Vp-p
: MD1
Approx.
1.86 Vp-p
: MD2
PB
200 ns: MD1
100 ns: MD2
200 ns: MD1
100 ns: MD2
Approx.
1.22 Vp-p
: MD1
Approx.
880 mVp-p
: MD2
3-11
3-12
3-6. MD SIGNAL PROCESS BLOCK DIAGRAM
Summary of Contents for MDDISCAM DCM-M1
Page 5: ...1 1 SECTION 1 GENERAL This section is extracted from in struction manual 3 866 152 11 DCM M1 ...
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Page 69: ...DCM M1 4 5 4 6 4 7 4 8 4 1 FRAME SCHEMATIC DIAGRAM FRAME ...
Page 96: ...DCM M1 4 115 4 113 4 114 ETHER INTERFACE ETHER ...