
Issue 11
© Solarflare Communications 2014
95
Solarflare Server Adapter
User Guide
The
lspci
command can be used to discover the currently negotiated PCIe lane width and speed:
lspci -d 1924: -vv
02:00.1 Class 0200: Unknown device 1924:0710 (rev 01)
...
Link: Supported Speed 2.5Gb/s, Width x8, ASPM L0s, Port 1
Link: Speed 2.5Gb/s, Width x8
CPU Speed Service
Most Linux distributions will have the
cpuspeed
service running by default. This service controls the
CPU clock speed dynamically according to current processing demand. For latency sensitive
applications, where the application switches between having packets to process and having periods
of idle time waiting to receive a packet, dynamic clock speed control may increase packet latency.
Solarflare recommend disabling the cpuspeed service if minimum latency is the main consideration.
The service can be disabled temporarily:
/sbin/service cpuspeed stop
The service can be disabled across reboots:
/sbin/chkconfig –level 12345 cpuspeed off
Memory bandwidth
Many chipsets use multiple channels to access main system memory. Maximum memory
performance is only achieved when the chipset can make use of all channels simultaneously. This
should be taken into account when selecting the number of DIMMs to populate in the server.
Consult the motherboard documentation for details.
Intel® QuickData
Intel® QuickData Technology allows recent Linux distributions to data copy by the chipset instead of
the CPU, to move data more efficiently through the server and provide fast, scalable, and reliable
throughput.
Enabling QuickData
• On some systems the hardware associated with QuickData must first be enabled (once
only) in the BIOS
• Load the QuickData drivers with
modprobe ioatdma
Server Motherboard, Server BIOS, Chipset Drivers
Tuning or enabling other system capabilities may further enhance adapter performance. Readers
should consult their server user guide. Possible opportunities include tuning PCIe memory controller
(PCIe Latency Timer setting available in some BIOS versions).
NOTE:
The Supported speed may be returned as 'unknown', due to older
lspci
utilities not
knowing how to determine that a slot supports PCIe Gen. 2.0/5.0 Gb/s or PCIe Gen 3.0/8,0 Gb/s.