Skyworks Si5332 Page 33 Manual Download

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Table 5.12. Fanout Mode Additive Jitter Performance Specifications

= V

DDA

= V

DD_DIG

= V

DD_XTAL

= 1.8 V to 3.3 V +10%/-5%, V

DDO

= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T

= –40 to 85 °C)

Parameter

Symbol

Test Condition

Typ

Max

Units

Additive Phase Jitter

156.25MHz,

12kHz-20MHz

LVDS (slow mode)

130 (LVDS slow)

170

fs RMS

156.25MHz,

12kHz-20MHz,

LVDS (fast mode)

120

150

fs RMS

156.25MHz,

12kHz-20MHz,

LVPECL

110

140

fs RMS

156.25MHz,

12kHz-20MHz,

HCSL

120

150

fs RMS

PCIe Gen3 / 4 Addi-

tive Phase Jitter

100MHz HCSL in-

put/outputs

Includes PLL BW 2–

4 MHz, CDR = 10

MHz

2, 3, 4, 5

fs RMS

Note:

1. Measured with differential input on CLKIN_2, bypassing the PLL to any output.
2. Skyworks' PCIe Clock Jitter Tool is used to obtain measurements for additive phase jitter. Additive Phase Jitter = sqrt(output jitter

- input jitter

). Input used is 100 MHz from Si5340.

3. Measurements on 100 MHz output use the template file in the PCIe Clock Jitter Tool.
4. For complete PCIe specifications, visit

www.pcisig.com

5. Input clock slew rate of 3.0 V/ns used for jitter measurements.

Si5332 Data Sheet • Electrical Specifications

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com

Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 16, 2021

Summary of Contents for Si5332

Page 1: ...w configuration using the ClockBuilder Pro Field Programmer Applications Servers Storage Search Acceleration Ethernet Switches Routers Small Cells Mobile Backhaul Fronthaul Print Imaging Communications Broadcast Video Test and Measurement Industrial Embedded Computing KEY FEATURES Any Frequency 6 8 12 output programmable clock generators Offered in three different package sizes supporting differen...

Page 2: ...Parts 18 3 9 I2C Serial Interface 18 3 10 In Circuit Programming 19 4 Register Map 20 5 Electrical Specifications 21 6 Pin Descriptions 37 6 1 Pin Descriptions 48 Pin 37 6 2 Pin Descriptions 40 Pin 42 6 3 Pin Descriptions 32 Pin 47 7 Package Outline 51 7 1 Si5332 6x6 mm 48 QFN Package Diagram External Crystal Versions Si5332A B C D 51 7 2 Si5332 6x6 mm 40 QFN Package Diagram External Crystal Versi...

Page 3: ...Land Pattern 64 8 4 Si5332E F G H L 48 LGA Land Pattern 66 8 5 Si5332E F G H L 40 LGA Land Pattern 68 8 6 Si5332E F G H L 32 LGA Land Pattern 70 9 Top Marking 72 10 Revision History 73 Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 3 Rev 1 3 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice N...

Page 4: ... per output LVDS LVPECL HCSL LVCMOS Low phase jitter 175 fs RMS embedded crystal 190 fs RMS external crystal PCIe Gen1 2 3 4 SRIS compliant 1 8 V 2 5 V 3 3 V core VDD Adjustable output output delay Multi profile configuration support Store up to 16 input output configurations in the same cus tom part number Independent glitchless on the fly output frequency changes Very low power consumption Indep...

Page 5: ...40 to 85 C Integer and Fractional mode Integer mode only Integer mode only Integer and Fractional mode Embedded Crystal or External Clock Integer and Fractional mode Integer mode only Integer mode only Integer and Fractional mode Frequency Synthesis Mode Integer and Fractional mode Ordering Part Number Input Type Output Clock Frequency Range Operating Temperature Range Si5332A 5MHz 333 33MHz Si533...

Page 6: ...50 MHz crystal or an embedded 50 MHz crystal for generating free running clocks or to an external clock CLKIN_2 CLKIN_2 or CLKIN_3 CLKIN_3 for generating synchronous clocks In free run mode the oscillator frequency is multiplied by the PLL and then divided down either by an integer divider or MultiSynth for fractional synthesis The Si5332 features user defined universal hardware input pins which c...

Page 7: ...OUT8b INT Bank C XTAL OSC Si5332A B C D External Crystal Si5332E F G H L Internal Crystal PLL INT CLKIN_3 CLKIN_3b CLKIN_2 CLKIN_2b INT Figure 3 1 Block Diagram for 12 Output Si5332 in 48 QFN LGA The Si5332 GM3 features Up to twelve differential clock outputs with six VDDO pins Seven user configurable HW input pins defined using ClockBuilder Pro Si5332 Data Sheet Functional Description Skyworks So...

Page 8: ... OSC CLKIN_2b Si5332A B C D External Crystal Si5332E F G H L Internal Crystal INT Figure 3 2 Block Diagram for 8 Output Si5332 in 40 QFN LGA The Si5332 GM2 features Up to eight differential clock outputs with six VDDO pins Seven user configurable HW input pins defined using ClockBuilder Pro Si5332 Data Sheet Functional Description Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales sk...

Page 9: ...ization tasks Communicating with the device through the serial interface is possible once this initialization period is complete The clock outputs will be squelched until the device initialization is done 3 3 Frequency Configuration The phase locked loop is fully integrated and does not require external loop filter components Its function is to phase lock to the selected input and provide a common...

Page 10: ...run mode 3 4 2 Input Clocks An input clock is available to synchronize the PLL when operating in synchronous mode This input can be configured as LVPECL LVDS or HCSL differential or LVCMOS The recommended input termination schemes are shown in the Si5332 Family Reference Manual Differential signals must be AC coupled Unused inputs can be disabled by register configuration 3 4 3 Input Selection The...

Page 11: ...clock outputs with dedicated VDDO pins each of which can be sourced from MultiSynth0 MultiSynth1 the input reference clock or one of the five INT dividers through the cross point MUX The remaining ten clock outputs are divided into Bank A Bank B Bank C and Bank D Each Bank of outputs can be sourced from MultiSynth0 MultiSynth1 the input reference clock or one of the five INT dividers through the c...

Page 12: ...nge should be verified for compatibility with the output Si5332 LVDS Output Driver Zo ZT 2 LVDS Receiver ZT Zo ZT 2 Figure 3 5 Standard LVDS Termination LVDS Receiver ZT 2 ZT 2 C Zo ZT 2 Zo ZT 2 Si5332 LVDS Output Driver Figure 3 6 Optional LVDS Termination Termination for 3 3 V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs The two different layou...

Page 13: ...R2 84Ω Input R4 125Ω R3 125Ω 3 3V Si5332 LVPECL Output Driver Figure 3 8 3 3 V LVPECL Output Termination Option 2 Si5332 Data Sheet Functional Description Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 13 Rev 1 3 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice November 16 2021 13 ...

Page 14: ...hown in Figure 3 9 2 5 V LVPECL Termination Example Option 1 on page 14 2 5V 2 5V 2 5V LVPECL Driver Zo 50 Ω Zo 50 Ω R1 62 5 Ω R2 62 5 Ω Input R4 250 Ω R3 250 Ω 2 5V RTT 29 5 Ω Si5332 LVPECL Output Driver Figure 3 9 2 5 V LVPECL Termination Example Option 1 2 5V 2 5V 2 5V LVPECL Driver Zo 50 Ω Zo 50 Ω R1 50Ω R2 50Ω Input R3 18Ω Si5332 LVPECL Output Driver Figure 3 10 2 5 V LVPECL Termination Examp...

Page 15: ... or 50 Ω HCSL Receiver Zo 42 5 Ω or 50 Ω Si5332 HCSL Output Driver Figure 3 11 HCSL Internal Termination Mode 1 71 V to 3 465 V OUTx OUTx Zo 42 5 Ω or 50 Ω HCSL Receiver Zo 42 5 Ω or 50 Ω RT Zo RT Zo Si5332 HCSL Output Driver Figure 3 12 HCSL External Termination Mode Si5332 Data Sheet Functional Description Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skywo...

Page 16: ...ble The universal hardware input pins can be programmed to operate as output enable OEb controlling one or more outputs Pin assignment is done using ClockBuilder Pro An output enable pin provides a convenient method of disabling or enabling the output drivers When the output enable pin is held high all designated outputs will be disabled When held low the designated outputs will be enabled 3 5 7 D...

Page 17: ...l hardware input pins are user configurable control input pins that can have one or more of the functions listed below assigned to them using ClockBuilder Pro Universal hardware input pins can be utilized for the following functions Table 3 2 Universal Hardware Input Pins Description Function SSEN_EN0 Spread spectrum enable on MultiSynth0 N0 SSEN_EN1 Spread spectrum enable on MultiSynth0 N1 FS_INT...

Page 18: ...different input source clock Multi Profile Si5332 has the ability to store multiple unique configurations in the same custom part number by enabling multi profile support in ClockBuilder Pro after selecting the desired Si5332 device The ClockBuilder Pro wizard guides users to enter the input output feature set needed for each individual profile configuration then compiles them together and assigns...

Page 19: ...ro Field Programmer CBPROG DON GLE and CBPro software See UG286 ClockBuilderPro Field Programmer Kit user s guide available on our web site for more information One important note The Si5332 core VDDs VDD_DIG VDDA and VDD_XTAL must be powered by 3 3 V during in circuit NVM programming VDD core voltages VDD_DIG VDDA VDD_XTAL must be 3 3 V for in circuit programming Using VDD core voltage lower than...

Page 20: ... descriptions and settings Si5332 Data Sheet Register Map Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 20 Rev 1 3 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice November 16 2021 20 ...

Page 21: ... Note 1 All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions Typical values apply at nominal supply voltages and an operating temperature of 25 C unless otherwise noted 2 All core voltages VDD_DIG VDDA VDD_XTAL must be connected to the same voltage Si5332 Data Sheet Electrical Specifications Skyworks Solutions Inc Phone 781 376 3000 Fax 781 37...

Page 22: ...mination resistors 2 Si5332 32 pin test configuration VDDD VDDA VDDI 1 8 V 2 2 5 V LVDS outputs enabled 156 25 MHz 2 1 8 V HCSL outputs enabled 100 MHz 2x 3 3 V LVCMOS outputs enabled 25 MHz Excludes power in termination resistors 3 Differential outputs terminated into a 100 Ω load 4 LVCMOS outputs measured into a 5 inch 50 Ω PCB trace with 4 pF load 50 50 100 OUT OUT IDDO Differential Output Test...

Page 23: ... VIH 0 8 VDD V Input Low Voltage VIL 0 2 VDD V Slew Rate 1 2 SR SF 20 80 0 75 V ns Duty Cycle DC 40 60 Input Capacitance CIN 2 3 5 6 pF Input Clock AC Coupled Input Clock on XA Frequency FIN 10 170 MHz Voltage Swing 1 Vpp Input Low Voltage VIL 0 2 x VDD V Slew Rate 1 2 SR SF 20 80 0 75 V ns Duty Cycle DC 40 60 Input Capacitance CIN 2 3 5 6 pF Notes 1 Imposed for jitter performance 2 Rise and fall ...

Page 24: ...n 5 3 1 for more detailed information Table 5 5 Embedded Crystal Specifications Parameter Symbol Test Condition Min Typ Max Units Initial Accuracy E F G H L Grades 1 fi Measured at 25 C at time of shipping 10 ppm Total Stability E F G H L Grades 40 C to 85 C 50 50 ppm Total Stability L Grade Only 25 C to 85 C 30 30 ppm Temperature Stability E F G H L Grades 40 C to 85 C 30 30 ppm Temperature Stabi...

Page 25: ...tance CIN 4 pF Pull up down Resistance RIN 50 kΩ Note 1 VDD indicates all core voltages VDD_DIG VDDA and VDD_XTAL which are required to all be using same nominal voltage Si5332 Data Sheet Electrical Specifications Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 25 Rev 1 3 Skyworks Proprietary Information Products and Product Information are Subj...

Page 26: ...Rate Edgr Notes 12 14 18 1 4 5 V ns HCSL Delta Tr Dtr Notes 14 17 18 135 ps HCSL Delta Tf Dtf Notes 14 17 18 125 ps HCSL Vcross Abs Vxa Notes 11 13 14 17 250 550 mV HCSL Delta Vcross Dvcrs Notes 14 17 140 mV HCSL Vovs Vovs Notes 14 17 VHIGH 300 mV HCSL Vuds Vuds Notes 14 17 VLOW 300 mV HCSL Vrng Vrng Notes 14 17 VHIGH 200 VLOW 200 mV Rise and Fall Times 20 to 80 tR tF LVDS fast mode 3 3 V or 2 5 V...

Page 27: ...owest crossing point to the highest regardless of which edge is crossing 10 Test configuration is Rs 33 2 Ω Rp 49 9 2 pF 11 Vcross rel Min and Max are derived using the following Vcross rel Min 0 250 0 5 Vhavg 0 700 Vcross rel Max 0 550 0 5 0 700 Vhavg 12 Measurement taken from Single Ended waveform 13 Measurement taken from differential waveform VLow Math function 14 Overshoot is defined as the a...

Page 28: ...e 5 trace CL 4 pf 0 75 1 3 ns Rise Fall Time 1 5 V 20 80 tR tF 50 Ω impedance 5 trace CL 4 pf 0 9 1 3 ns CMOS Output Resistance Single Strength 3 3 V 46 Ω 2 5 V 48 Ω 1 8 V 53 Ω 1 5 V 58 Ω CMOS Output Resistance Double Strength 3 3 V 23 Ω 2 5 V 24 Ω 1 8 V 27 Ω 1 5 V 29 Ω CMOS Output Voltage VOH 4 mA load VDDO 0 3 V VOL 4 mA load 0 3 V Duty Cycle DC XO and PLL mode 45 55 Si5332 Data Sheet Electrical...

Page 29: ...KDEV MultiSynth Output 250 MHz 0 1 2 5 0 5 Spread Frequency Deviation2 SSDEV MultiSynth Output 250 MHz 0 4 0 45 0 5 Spread Spectrum Modulation Rate2 3 SSMOD MultiSynth Output 250 MHz 30 31 5 33 kHz Notes 1 Update rate via I2C is also limited by the time it takes to perform a write operation 2 The maximum step size is only limited by the register lengths however the MultiSynth output frequency must...

Page 30: ...ER of 1e 12 3 5 ps Pk Pk JCC 3 1 ps Pk JPER N 10 000 cycles Integer or Fractional Mode 2 3 Measured in the time domain Performance is limited by the noise floor of the equipment 12 ps Pk Pk JCC 11 ps Pk Jitter Generation Locked to Embedded 50 MHz Crystal JGEN INT Mode 12 kHz 20 MHz 1 2 175 215 fs RMS FRAC DCO Mode 12 kHz 20 MHz 3 5 250 fs RMS JPER Derived from integrated phase noise at a BER of 1e...

Page 31: ...due to the nature of LVCMOS outputs If your configuration implements any LVCMOS output and any output is required to have jitter less than 3 ps RMS contact Skyworks for support to validate your configuration and ensure the best jitter performance 5 FRAC jitter generation test conditions fOUT 150 MHz LVPECL 6 Measured at 156 25 MHz carrier frequency Carrier power of 1 5 dBm 100 mVpp sine wave noise...

Page 32: ... 1 ps RMS On 0 26 0 36 ps RMS PCIe Gen4 0 SRIS Includes PLL BW 4 MHz Peaking 2dB 1dB Td 12 ns CDR 10 MHz 2 3 On 0 31 0 36 ps RMS PCIe Gen5 0 Com mon Clock Includes PLL BW 500 kHz 1 8 MHz CDR 20 MHz Off 0 025 0 04 Ps RMS On 0 1 0 15 Ps RMS PCIe Gen5 0 SRIS Includes PLL BW 500 kHz 1 8 MHz CDR 20 MHz On 0 08 0 1 Ps RMS Notes 1 All jitter data in this table is based upon all output formats being diffe...

Page 33: ...S Note 1 Measured with differential input on CLKIN_2 bypassing the PLL to any output 2 Skyworks PCIe Clock Jitter Tool is used to obtain measurements for additive phase jitter Additive Phase Jitter sqrt output jitter2 input jitter2 Input used is 100 MHz from Si5340 3 Measurements on 100 MHz output use the template file in the PCIe Clock Jitter Tool 4 For complete PCIe specifications visit www pcis...

Page 34: ... to Case θJC 14 1 Thermal Resistance Junction to Board θJB 11 4 ψJB Still Air 3 4 Thermal Resistance Junction to Top Center ψJT 0 4 Si5332 32 QFN Thermal Resistance Junction to Ambient θJA Still Air 28 4 C W Air Flow 1 m s 24 Air Flow 2 m s 23 Thermal Resistance Junction to Case θJC 18 5 Thermal Resistance Junction to Board θJB 15 1 ψJB Still Air 7 Thermal Resistance Junction to Top Center ψJT 0 5...

Page 35: ... Thermal Resistance Junction to Board θJB 18 9 ψJB Still Air 18 9 Thermal Resistance Junction to Top Center ψJT 0 4 Si5332 32 LGA Thermal Resistance Junction to Ambient θJA Still Air 35 21 C W Air Flow 1 m s 32 9 Air Flow 2 m s 31 7 Thermal Resistance Junction to Case θJC 19 8 Thermal Resistance Junction to Board θJB 24 3 ψJB Still Air 24 3 Thermal Resistance Junction to Top Center ψJT 0 5 Note 1 ...

Page 36: ...damage may occur if the absolute maximum ratings are exceeded Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet Exposure to absolute maximum rating conditions for extended periods may affect device reliability 2 For more packaging information go to https www skyworksinc com product_certificate aspx 3 The device is compliant with...

Page 37: ...DO3 49 GND Input2 Input3 CLKIN_2 CLKIN_2b VDDA Input5 OUT6b OUT6 OUT5b OUT5 OUT4b OUT4 OUT3b OUT3 OUT1b OUT1 VDDO0 OUT0b OUT0 Input4 SCLK SDATA CLKIN_3 CLKIN_3b VDDO1 OUT2b OUT2 VDDO2 OUT8b OUT8 Input7 Figure 6 1 48 QFN Si5332 Data Sheet Pin Descriptions Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 37 Rev 1 3 Skyworks Proprietary Information ...

Page 38: ... both the CLKIN_3 and CLKIN_3b inputs are unused and powered down then both inputs can be left floating ClockBuilder Pro will power down an input that is set as Unused 8 CLKIN_3b I 9 VDDA P Core Supply Voltage Connect to 1 8 3 3 V See the Si5332 Family Reference Manual for power supply filtering recom mendations Must be connected to same voltage as VDD_DIG and VDD_XTAL 10 INPUT1 I Universal HW Inp...

Page 39: ...DDO1 P Supply Voltage 1 8 3 3 V or 1 5 V for CMOS only for OUT1 and OUT2 See the Si5332 Family Reference Manual for power supply filtering recom mendations Leave VDDOx pins of unused output drivers unconnected An alternate option is to connect the VDDOx pin to a power supply and disable the output driver to minimize current consumption 21 OUT2b O Output Clock These output clocks support a programm...

Page 40: ...d outputs should be left unconnected 32 OUT6 O 33 OUT7b O Output Clock These output clocks support a programmable signal swing common mode voltage Desired output signal format is configurable using register control Termination recommendations are provided in 3 5 2 Differential Output Ter minations and 3 5 3 LVCMOS Output Terminations Unused outputs should be left unconnected 34 OUT7 O 35 OUT8b O O...

Page 41: ...for CMOS only for OUT10 and OUT11 See the Si5332 Family Reference Manual for power supply filtering recom mendations Leave VDDOx pins of unused output drivers unconnected An alternate option is to connect the VDDOx pin to a power supply and disable the output driver to minimize current consumption 45 OUT10b O Output Clock These output clocks support a programmable signal swing common mode voltage ...

Page 42: ... OUT7 OUT7b VDDO4 OUT6 OUT6b Input4 Input5 VDDO2 Input2 Input3 OUT3b OUT3 OUT2b OUT2 VDDO3 2 3 4 5 6 7 8 9 10 1 CLKIN_3 CLKIN_3b OUT4b OUT4 OUT5b OUT5 Input7 Figure 6 2 40 QFN Si5332 Data Sheet Pin Descriptions Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 42 Rev 1 3 Skyworks Proprietary Information Products and Product Information are Subject...

Page 43: ...r input termination options These pins are high impedance and must be terminated externally If both the CLKIN_3 and CLKIN_3b inputs are un used and powered down then both inputs can be left floating ClockBuilder Pro will power down an input that is set as Unused 8 CLKIN_3b I 9 VDDA P Core Supply Voltage Connect to 1 8 3 3 V See the Si5332 Family Reference Manual for power supply filtering recom me...

Page 44: ...r definable through ClockBuilder Pro Refer to 3 7 Universal Hardware Input Pins for a list of definitions that hardware input pins can be used for 20 INPUT3 I Universal HW Input pin This hardware input pin is user definable through ClockBuilder Pro Refer to 3 7 Universal Hardware Input Pins for a list of definitions that hardware input pins can be used for 21 OUT2b O Output Clock These output cloc...

Page 45: ... Supply Voltage 1 8 3 3 V or 1 5 V for CMOS only for OUT6 See the Si5332 Family Reference Manual for power supply filtering recom mendations Leave VDDOx pins of unused output drivers unconnected An alternate option is to connect the VDDOx pin to a power supply and disable the output driver to minimize current consumption 34 OUT6b O Output Clock These output clocks support a programmable signal swi...

Page 46: ...Ox pin to a power supply and disable the output driver to minimize current consumption 41 GND PAD P Ground Pad This pad provides electrical and thermal connection to ground and must be connected for proper operation Si5332 Data Sheet Pin Descriptions Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 46 Rev 1 3 Skyworks Proprietary Information Prod...

Page 47: ...s accept both differential and single ended clock signals Refer to Section 3 4 2 Input Clocks for input termination options These pins are high impedance and must be terminated externally If both the CLKIN_2 and CLKIN_2b inputs are un used and powered down then both inputs can be left floating ClockBuilder Pro will power down an input that is set as Unused 3 CLKIN_2b I 4 VDD_XTAL P Voltage supply ...

Page 48: ...d common mode voltage Desired output signal format is configurable using register control Termination recommendations are provided in 3 5 2 Differential Out put Terminations and 3 5 3 LVCMOS Output Terminations Unused outputs should be left unconnected 12 OUT0 O 13 VDDO0 P Supply Voltage 1 8 3 3 V or 1 5 V for CMOS only for OUT0 See the Si5332 Family Reference Manual for power supply filtering rec...

Page 49: ...o connect the VDDOx pin to a power supply and disable the output driver to minimize current consumption 24 INPUT3 I Universal HW Input pin This hardware input pin is user definable through ClockBuilder Pro Refer to Section 3 7 Universal Hardware Input Pins for a list of definitions that hardware input pins can be used for 25 VDDO4 P Supply Voltage 1 8 3 3 V or 1 5 V for CMOS only for OUT4 See the ...

Page 50: ...he Si5332 Family Reference Manual for power supply filtering recom mendations Leave VDDOx pins of unused output drivers unconnected An alternate option is to connect the VDDOx pin to a power supply and disable the output driver to minimize current consumption 33 GND PAD P Ground Pad This pad provides electrical and thermal connection to ground and must be connected for proper operation Si5332 Data...

Page 51: ...N Table 7 1 Package Dimensions Dimension Min Nom Max A 0 80 0 85 0 90 A1 0 00 0 02 0 05 b 0 15 0 20 0 25 D 6 00 BSC D2 3 5 3 6 3 7 e 0 40 BSC E 6 00 BSC E2 3 5 3 6 3 7 L 0 30 0 40 0 50 aaa 0 10 bbb 0 10 ccc 0 10 ddd 0 05 eee 0 08 Si5332 Data Sheet Package Outline Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 51 Rev 1 3 Skyworks Proprietary Inf...

Page 52: ...tate Outline MO 220 4 Recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Body Components Si5332 Data Sheet Package Outline Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 52 Rev 1 3 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice November 16 2021 52 ...

Page 53: ...C E2 4 35 4 50 4 65 L 0 30 0 40 0 50 aaa 0 10 bbb 0 10 ccc 0 08 ddd 0 10 eee 0 05 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This drawing conforms to the JEDEC Outline MO 220 4 Recommended card reflow profile is per the JEDEC IPC J STD 020D specification for Small Body Components Si5332 Data Sheet Package Outline ...

Page 54: ...7 3 Package Dimensions Dimension MIN NOM MAX A 0 80 0 85 0 90 A1 0 00 0 02 0 05 A3 0 20 REF b 0 18 0 25 0 30 D E 4 90 5 00 5 10 D2 E2 3 40 3 50 3 60 e 0 50 BSC L 0 30 0 40 0 50 K 0 20 R 0 09 0 14 aaa 0 15 bbb 0 10 ccc 0 10 Si5332 Data Sheet Package Outline Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 54 Rev 1 3 Skyworks Proprietary Informatio...

Page 55: ...dy Components 7 4 Si5332 6x6 mm 48 LGA Package Diagram Embedded Crystal Versions Si5332E F G H L The figure below illustrates the package details for the Si5332E F G H L in 48 LGA The table below lists the values for the dimensions shown in the illustration Figure 7 4 48 Pin LGA Si5332 Data Sheet Package Outline Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www s...

Page 56: ...EP Count n1 4 Package Edge Tolerance aaa 0 1 Mold Flatness bbb 0 1 Coplanarity ddd 0 08 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This drawing conforms to the JEDEC Solid State Outline MO 220 4 Recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Body Components Si5332 Data Sheet...

Page 57: ...The table below lists the values for the dimensions shown in the illustration Figure 7 5 40 Pin LGA Si5332 Data Sheet Package Outline Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 57 Rev 1 3 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice November 16 2021 57 ...

Page 58: ... EP Count n1 4 Package Edge Tolerance aaa 0 1 Mold Flatness bbb 0 1 Coplanarity ddd 0 08 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This drawing conforms to the JEDEC Solid State Outline MO 220 4 Recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Body Components Si5332 Data Shee...

Page 59: ...0 32 0 37 0 42 L1 0 10 REF aaa 0 10 bbb 0 10 ccc 0 08 ddd 0 10 eee 0 08 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This drawing conforms to the JEDEC Solid State Outline MO 220 4 Recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Body Components Si5332 Data Sheet Package Outline...

Page 60: ...on mm C1 5 90 C2 5 90 e 0 40 BSC X1 0 20 Y1 0 85 X2 3 60 Y2 3 60 Si5332 Data Sheet PCB Land Pattern Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 60 Rev 1 3 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice November 16 2021 60 ...

Page 61: ...paste release 2 The stencil thickness should be 0 125 mm 5 mils 3 The ratio of stencil aperture to land pad size can be 1 1 for all perimeter pads 4 The stencil aperture to center land pads size recommendation is 70 paste coverage Card Assembly 1 A No Clean Type 3 solder paste is recommended 2 The recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Body Component...

Page 62: ...5 90 C2 5 90 e 0 50 BSC X1 0 30 Y1 0 85 X2 4 65 Y2 4 65 Si5332 Data Sheet PCB Land Pattern Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 62 Rev 1 3 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice November 16 2021 62 ...

Page 63: ...paste release 2 The stencil thickness should be 0 125 mm 5 mils 3 The ratio of stencil aperture to land pad size can be 1 1 for all perimeter pads 4 The stencil aperture to center land pad size recommendation is 70 paste coverage Card Assembly 1 A No Clean Type 3 solder paste is recommended 2 The recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Body Components...

Page 64: ...ure 8 3 32 QFN Land Pattern Table 8 3 PCB Land Pattern Dimensions Dimension mm C1 4 90 C2 4 90 e 0 50 BSC X1 0 30 Y1 0 85 X2 3 60 Y2 3 60 Si5332 Data Sheet PCB Land Pattern Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 64 Rev 1 3 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice November 16 ...

Page 65: ...paste release 2 The stencil thickness should be 0 125 mm 5 mils 3 The ratio of stencil aperture to land pad size can be 1 1 for all perimeter pads 4 The stencil aperture to center land pad size recommendation is 70 paste coverage Card Assembly 1 A No Clean Type 3 solder paste is recommended 2 The recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Body Components...

Page 66: ... 5 52 C2 5 52 e 0 40 BSC X1 0 20 Y1 0 50 X2 2 60 Y2 2 60 Si5332 Data Sheet PCB Land Pattern Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 66 Rev 1 3 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice November 16 2021 66 ...

Page 67: ...stencil thickness should be 0 125 mm 5 mils 3 The ratio of stencil aperture to land pad size can be 1 1 for all perimeter pads 4 The package e pad is partitioned as a 2x2 array The stencil aperture to land pad size recommendation is 70 paste coverage Card Assembly 1 A No Clean Type 3 solder paste is recommended 2 The recommended card reflow profile is per the JEDEC IPC J STD 020 specification for ...

Page 68: ... 5 52 C2 5 52 e 0 50 BSC X1 0 30 Y1 0 50 X2 2 60 Y2 2 60 Si5332 Data Sheet PCB Land Pattern Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 68 Rev 1 3 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice November 16 2021 68 ...

Page 69: ...stencil thickness should be 0 125 mm 5 mils 3 The ratio of stencil aperture to land pad size can be 1 1 for all perimeter pads 4 The package e pad is partitioned as a 2x2 array The stencil aperture to land pad size recommendation is 70 paste coverage Card Assembly 1 A No Clean Type 3 solder paste is recommended 2 The recommended card reflow profile is per the JEDEC IPC J STD 020 specification for ...

Page 70: ...gure 8 6 32 LGA Land Pattern Table 8 6 PCB Land Pattern Dimensions Dimension mm C1 4 50 C2 4 50 e 0 50 BSC X1 0 30 Y1 0 45 X2 2 20 Y2 2 20 Si5332 Data Sheet PCB Land Pattern Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 70 Rev 1 3 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice November 16...

Page 71: ...der paste release 2 The stencil thickness should be 0 125 mm 5 mils 3 The ratio of stencil aperture to land pad size can be 1 1 for all perimeter pads 4 The stencil aperture to land pad size recommendation is 70 paste coverage Card Assembly 1 A No Clean Type 3 solder paste is recommended 2 The recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Body Components Si...

Page 72: ...n Rxxxxx R Product revision see ordering guide for current revision xxxxx Customer specific NVM sequence number NVM code assigned for custom factory pre programmed devices using ClockBuilder Pro See Ordering Guide for more information 3 TTTTTT Manufacturing trace code 4 YYWW Year YY and work week WW of package assembly Si5332 Data Sheet Top Marking Skyworks Solutions Inc Phone 781 376 3000 Fax 781...

Page 73: ...n mode and swing specifications into slow and fast mode Updated HCSL Tr Tf max specification from 400 ps to 420 ps Increased max output frequency range to 333 33 MHz Added package thermal characteristics table for E F G H embedded crystal grade devices Revision 1 0 February 2018 Updated Si5332 5x5 mm 32 QFN package diagram for external crystal versions Updated Si5332 32 QFN land pattern Updated ji...

Page 74: ...RECIPIENT OF MATERIALS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Skyworks products are not intended for use in medical lifesaving or life sustaining applications or other equipment in which the failure of the Skyworks products could lead to personal injury death physical or environmental damage Skyworks customers using or selling Skyworks products for use in such applications do so at the...

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