62
SDRCLK Control
Enables you to set the phase of the SDRCLK that leads the SDCLK.
"
The choice: +1.0ns, +0.5ns, 0.0ns, -0.5ns, -1.0ns, -1.5ns, -2.0ns,
-2.5ns, -3.0ns, -3.5ns, -4.0ns, -4.5ns, -5.0ns, -5.5ns,
-6.0ns, -6.5ns.
SDRCLK Control CS#/CKE
Enables you to set the phase of the SDWCLK used for CS#/CKE signals
that lead the SDCLK.
"
The choice: +5.0ns, +4.5ns, +4.0ns, +3.5ns, +3.0ns, +2.5ns,
+2.0ns, +1.5ns, +1.0ns, +0.5ns, 0.0ns, -0.5ns, -1.0ns,
-1.5ns, -2.0ns, -2.5ns.
SDRCLK Control MA/SRAS
Enables you to set the phase of the SDWCLK used for MA/SRAS#/
SCAS#/RAMW# signals that lead the SDCLK.
"
The choice: +5.0ns, +4.5ns, +4.0ns, +3.5ns, +3.0ns, +2.5ns,
+2.0ns, +1.5ns, +1.0ns, +0.5ns, 0.0ns, -0.5ns, -1.0ns,
-1.5ns, -2.0ns, -2.5ns.
SDRCLK Control Hi DQM/MD
Enables you to set the phase of the SDWCLK used for high DQM[7:4]/
MD[63:32] signals that lead the SDCLK.
"
The choice: +5.0ns, +4.5ns, +4.0ns, +3.5ns, +3.0ns, +2.5ns,
+2.0ns, +1.5ns, +1.0ns, +0.5ns, 0.0ns, -0.5ns, -1.0ns,
-1.5ns, -2.0ns, -2.5ns.
SDRCLK Control Lo DQM/MD
Enables you to set the phase of the SDWCLK used for Lo DQM[3:0]/
MD[31:0] signals that lead the SDCLK.
"
The choice: +5.0ns, +4.5ns, +4.0ns, +3.5ns, +3.0ns, +2.5ns,
+2.0ns, +1.5ns, +1.0ns, +0.5ns, 0.0ns, -0.5ns, -1.0ns,
-1.5ns, -2.0ns, -2.5ns.
Press
Esc
to close the Advanced DRAM Control 2 sub-menu and
return to the Advanced Chipset Features page.
