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Dram Background Command
When the delay is set at 1T, background commands are issued 1 clock
cycle behind the memory address (MA) which has been issued. When
set to normal, background commands and MAs are issued at the same
time.
"
The choice: Normal, Delay 1T.
LD-Off Dram RD/WR Cycles
When the delay is set at 1T, memory read and write commands are
issued 1 clock cycle behind the memory address (MA) which has been
issued. When set to Normal, read/write commands and MAs are issued
at the same time. Press
Esc
to close the Advanced DRAM Control 1 sub-
menu and return to the Advanced Chipset Features page.
"
The choice: Normal, Delay 1T.
Press
Esc
to close the Advanced DRAM Control 1 sub-menu and
return to the Advanced Chipset Features page.
Advanced DRAM Control 2
Scroll to Advanced DRAM Control 2 and press <Enter> to view the
following screen:
SDRAM CAS Latency
Enables you to select the CAS latency time in HCLKs of 2/2 or 3/3. The
value is set at the factory depending on the DRAM installed. Do not
change the values in this field unless you change specifications of the
installed DRAM or the installed CPU.
"
The choice: SPD, 2T, 3T.
