UP-3301US
CIRCUIT DESCRIPTION
– 53 –
2-5. VGA controller (MN89303A)
1) Pin Configuration
2) Block diagram
1
XIN
2
GND
3
AEN
4
/SBEH
5
/IOWR
6
/IORD
7
/SMEMW
8
/SMEMR
9
A21
10
A20
11
SA19
12
13
SA17
14
SA16
15
SA15
16
SA14
17
SA13
18
SA12
19
SA11
20
SA10
21
SA9
22
SA8
23
SA7
24
SA6
25
SA5
26
SA4
27
SA3
28
SA2
29
SA1
30
SA0
31
32
12
8
XO
12
7
12
6
MINTEST
12
5
TEST
12
4
RESET
12
3
VDD
12
2
GND
12
1
MD0
12
0
MD1
11
9
MD2
11
8
MD3
11
7
MD4
11
6
MD5
11
5
MD6
11
4
MD7
11
3
MD8
11
2
MD9
11
1
VDD
11
0
GND
10
9
MD10
10
8
MD11
10
7
MD12
10
6
MD13
10
5
MD14
10
4
MD15
10
3
/WE
10
2
/LCAS
10
1
/UCAS
10
0
/RAS
99
VDD
98
GND
97
MA
0
33
GND
34
VDD
35
SD15
36
SD14
37
SD13
38
SD12
39
GND
40
SD11
41
SD10
42
SD9
43
VDD
44
SD8
45
SD7
46
SD6
47
GND
48
SD5
49
SD4
50
SD3
51
SD2
52
SD1
53
SD0
54
GND
55
VDD
56
IOC
HRDY
57
/MEMCS16
58
/IOCS16
59
GND
60
VDD
61
DCLK
62
DISP
63
LP
64
FP
GND
SA18
/BIOSEN
/REFRESH
96
MA1
95
MA2
94
MA3
93
MA4
92
MA5
91
MA6
90
MA7
89
MA8
88
MA9
87
VDD
86
GND
85
84
LCDON
83
BACKON
82
LD0
81
LD1
80
LD2
79
LD3
78
LD4
77
LD5
76
LD6
75
LD7
74
VDD
73
GND
72
UD0
71
UD1
70
UD2
69
UD3
68
UD4
67
UD5
66
65
LOGICON
UD6
UD7
1
XIN
RESET
TEST/MINTEST
124
126/125
ADDRESS[21:0]
3
LCD panel
controller
UD[7:0]
LD[7:0]
BACKON
LCDON
83
FO
DISP
DCLK
LOGICON
84
85
63
64
62
LP
61
SD[15:0]
AEN
SBHE
IOWR
IORD
SMEMW
SMEMR
IOCHRDY
REFRESH
MEMCS16
IOCS16
4
5
6
7
8
56
32
57
58
Host
interface
LCD/CRT
controller
Gray scale
engine
Memory
write
buffer
RAM table
Hardware
cursor
Attributer
Video FIFO
Memory
interface
Access
attributer
Graphics
controller
MA[9:0]
MD[15:0]
RAS
UCAS
LCAS
WE
BIOSEN
100
101
102
103
31
Summary of Contents for UP-3301
Page 91: ...UP 3301US PWB LAYOUT 89 CHAPTER 9 PWB LAYOUT 1 MAIN PWB A side ...
Page 92: ...UP 3301US PWB LAYOUT 90 B side 8 CUSTOMER DISPLAY PWB ...
Page 93: ...UP 3301US PWB LAYOUT 91 2 IR PWB 3 LCD PWB A Side B Side 4 INVERTER PWB A Side B Side ...
Page 94: ...UP 3301US PWB LAYOUT 92 5 MOTHER PWB 6 N F PWB 7 TOUCH PANEL PWB ...
Page 95: ...UP 3301US PWB LAYOUT 93 ...
Page 111: ......