
1-22
Factory-Set Logic
Date Code 20020215
SEL-351R Instruction Manual
DWG: M351R082
Relay
Word
Bits
51P1
51P2
51G1
51G2
51N1
51N2
At least one fast curve or
delay curve is picked up
Ground current above cold
load ground min. trip
(see Figure 3.9)
Cold load pickup scheme
actively engaged for SEF
element (see Figure 1.4)
Ground current above cold
load ground min. trip
(see Figure 3.11)
SEF element
operates on cold
load ground min.
trip
67N3TC
Input into
67N3T logic
(see Figure 3.8)
GROUND ENABLED
operator control ON
(see Figure 1.41)
50N5
SV12
50G5
LT1
SEF element
operates on cold
load ground min.
trip
Figure 1.18: SEF Element Enable/Disable Logic
T
RIP
L
OGIC
See Figure 1.19. The overcurrent elements in Figure 1.19 are controlled by the logic in
Figure 1.15 through Figure 1.18. Other trip logic details:
•
If setting Min. trip - ground is set below 0.1 Amp secondary, 51N1T and 51N2T operate
as Fast curve - ground and Delay curve - ground, respectively (51G1T and 51G2T are
turned off automatically). Otherwise, 51G1T and 51G2T operate as Fast curve - ground
and Delay curve - ground, respectively (51N1T and 51N2T are turned off automatically).
•
If setting High current trip - ground is set effectively below 0.05 Amp secondary, 67N2T
operates as High current trip - ground (67G2T is turned off automatically). Otherwise,
67G2T operates as High current trip - ground (67N2T is turned off automatically).
Figure 1.19 propagates into the trip logic (see Figure 5.1). The trip signal output (Relay Word
bit TRIP) is then assigned to the HV FET trip output with SEL
OGIC
recloser control trip setting
(see Figure 7.30):
RCTR = TRIP
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