Date Code 20020215
Inputs, Outputs, Timers, and Other Control Logic
7-15
SEL-351R Instruction Manual
For example in Figure 7.13, if:
LT1 = logical 0
input IN104 is routed to setting SET1 (as discussed previously):
SET1 = /IN104 = rising edge of input IN104
If input IN104 is then asserted for a few cycles by the SCADA contact (see Pulse 1 in
Figure 7.14), SET1 is asserted to logical 1 for one processing interval. This causes latch bit LT1
to change state to:
LT1 = logical 1
the next processing interval.
With latch bit LT1 now at logical 1 for the next processing interval, input IN104 is routed to
setting RST1 (as discussed previously):
RST1 = /IN104 = rising edge of input IN104
This would then appear to enable the “reset” input (setting RST1), the next processing interval.
However, the “rising edge” condition occurred in the preceding processing interval, causing
/IN104 to then deassert to logical 0. So, since /IN104 is now at logical 0, setting RST1 does not
assert, even though input IN104 remains asserted for at least a few cycles by the SCADA
contact.
If the SCADA contact deasserts and then asserts again (new rising edge—see Pulse 2 in
Figure 7.14), the “reset” input (setting RST1) asserts and latch bit LT1 deasserts back to
logical 0 again. Thus, each individual assertion of input IN104 (Pulse 1, Pulse 2, Pulse 3, and
Pulse 4 in Figure 7.14) changes the state of latch control switch just once.
Note:
Refer to preceding subsection
and Figure 7.1. Relay Word bit
IN104 shows the state of optoisolated input IN104 after the input pickup/dropout
debounce timer IN104D. Thus, when using Relay Word bit IN104 in Figure 7.11 and
Figure 7.12 and associated SEL
OGIC
control equations, keep in mind any time delay
produced by the input pickup/dropout debounce timer IN104D.
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