5. System Diagram
5. System Diagram
5.1. Block Diagram
DDR3
16b it(O n d ie )
128MB
Kin g b ird SMPS(NEW)
PO WER
CO RD
E
EP ROM
S CX-4729FD/FW
:64KB
S e ria l Nor
: 20MB
(
16MB + 4MB)
DC-DC Co n ve rte r
SN1001043 : 1.2V/1.5V/3.3V
MII
(AC201A1)
En g in e
S P I
DDR
C o n tr o l
I2C
MAC
UAR T
C3-Ne xt
VIDEO CONTROL
P WM C LOC K US B 2.0
DEVE K UNIT
CRUM
HVP S : EP & THV High Volta ge output
Cove r ope n de te c t
Binfull/ Re gi/ fe e d/ P _e m pty s e ns or
Crum IF / P ic kup & re gi c lutc h
R
E
S
E
T
LSU
Vid e o
IF
ABC Chip
(S W3304B)
I
2C
Motor – S te p(A4984)
-
Sc a n
,
ADF (2)
F
a n (1)
-. MAIN
,
-. Ma in : P _Exit S e ns or
FDC642
24VS
TR(
x2)
S
ys te m Bo a rd
WLAN IF
W
-m ode l only
FUS ER UNIT
Co n ta c t
Th e rm is to r
850W la m p
Th e rm o s ta t
Motor IC-Le s s (2)
-
BLDC MAIN (1)
-
LS U P -Motor (1)
5
V
CRUM IF
S DIO
FET(
x2)
5
V
_
S
M
P
S
2
4
V
_
S
M
P
S
Mic ro S/W
(h vp s )
3
_
3
V
_
C
_
O
P
E
N
1
CIS IF
LAFE1001
MODEM IF
- Loc a l bus (A 7bit
,
D 8bit)
RTC
CR2032(T.B.D)
CIS LED Drive r(AK7864)
S e ns or (4)
-. ADF Cove r
,
ADF_P _DET
,
ADF_P _P OS
,
S c a n hom e
Motor S te p(2)
-
SCAN
,
ADF
S
pe a ke r
MODEM IF
-. Cone xa nt
UI
2
-Line LCD OP E
LS U Vide o
-. Dua l be a m
S
P
I
US B2.0 De vic e
U
A
R
T
Em b e d d e d US B
G
P IO o r UAR T
C
IS Module
5-1
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