S3F84B8_UM_REV 1.00
4 CONTROL REGISTERS
4-5
4.1.1 ADCON — A/D CONVERTER CONTROL REGISTER: FAH, BANK0
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0 0 0 0 0 0 0 0
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W
A/D Converter Input Pin Selection Bits
0 0 0 ADC0
(P2.0)
0 0 1 ADC1
(P2.1)
0 1 0 ADC2
(P2.2)
0 1 1 ADC3
(P2.3)
1 0 0 ADC4
(P2.4)
1 0 1 ADC5
(P2.5)
1 1 0 ADC6
(P2.6)
.7–.5
1 1 1 ADC7
(P2.7)
AD Conversion Completion Interrupt Enable Bit
0
Disables ADC Interrupt.
.4
1
Enables ADC Interrupt.
A/DC Interrupt Pending Bit (EOC)
0
No interrupt is pending, conversion is in progress
(clears pending bit when write).
.3
1
Interrupt is pending, conversion has completed (no effect when write).
Clock Source Selection Bit (Note)
0 0 f
OSC
/8 (f
OSC
10MHz)
0 1 f
OSC
/4 (f
OSC
10MHz)
1 0 f
OSC
/2 (f
OSC
8MHz)
.2–.1
1 1 f
OSC
/1 (f
OSC
4MHz)
Conversion Start Bit
0 No
effect
.0
1
Starts A/D conversion.
NOTE:
Maximum ADC clock input = 4MHz.