S3F84B8_UM_REV 1.00
6 INSTRUCTION SET
6-36
6.3.24 DI — DISABLE INTERRUPTS
DI
Operation
: SYM
(0)
0
Bit zero of the system mode control register, SYM.0, is cleared to “0”, globally disabling all
interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits,
but the CPU will not service them if interrupt processing is disabled.
Flags
:
No flags are affected.
Format
:
Bytes Cycles
Opcode
(Hex)
opc
1 4 8F
Example
:
Given SYM = 01H:
DI
If the value of SYM register is 01H, statement “DI” leaves the new value 00H in register and
clears SYM.0 to “0”, disabling interrupt processing.
Before changing IMR, interrupt pending, and interrupt source control register, ensure that all
interrupts are disabled.