Using PEEDI
[ACTIONS]
AUTORUN = 2
1 = erase_program_verify
2 = prog_http
[erase_program_verify]
flash prog tftp://192.168.1.41/main_romram.bin bin 0x400000
flash verify tftp://192.168.1.41/main_romram.bin bin 0x400000
[prog_http]
flash prog
http://192.168.1.41/main_romram.bin bin 0x400000 erase
3.6 CPU specific considerations
3.6.1 Philips LPC2000 family
To successfully connect to a LPC2000 device the pull-down resistor that enables the JTAG interface
must not be more than 1k, because PEEDI has internal 10k pull-ups.
Because the JTAG clock is synchronized to the internal CPU clock it is recommended to use
adaptive JTAG clock or clock up to 1MHz for normal work (the second argument of the
JTAG_CLOCK parameter).
3.6.2 ST STM32 family
Use the following commands in the target INIT script to enable SWO stimulus output:
; init SWO
mem wr 0xE0042004 0x20 ; TRACE_IOEN (async mode)
mem wr 0xE0040010 2 ; TPIU_ACPR = 1 (SWO prescale 2)
mem wr 0xE00400F0 1 ; TPIU_SPPR = 1 (SWO Manchester
encoding)
mem wr 0xE0040304 0 ; TPIU: disable formatter
mem wr 0xE0000FB0 0xC5ACCE55 ; ITM: unlock ITM_TCR
mem wr 0xE0000E80 0x10009 ; ITM_TCR: TXENA +
TraceBusID=0x1
mem wr 0xE0000E40 0xF ; en. all tracing ports
mem wr 0xE0000E00 0xFFFFFFFF ; en. all stimulus ports
PEEDI supports only Manchester SWO encoding up to 66MHz.
PEEDI checks for new incoming telnet connection only when the target CPU is halted.
If the SWO functionality seems unstable, lower the CPU clock or increase the SWO prescaler, both
of these will result in lower SWO clock.
PEEDI User’s Manual
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