Using PEEDI
CORE_MEMMAP
Synopsis:
CORE_MEMMAP = <start_addr>, <end_addr>
Description:
Defines a valid memory region. Up to 32 regions can be defined in the target
configuration file. When even one region is defined, PEEDI begins to check every
memory access operation if it falls into a defined memory region. If the memory
operation is out of the defined regions, PEEDI interrupts the operation and issues an
error. This is made so, because when an access is made to an invalid memory address
via the BDM, the ColdFire CPU refuses to respond to any further memory operations
until reset.
Section PLATFORM_BLACKFIN
This section describes the Blackfin cores connected to PEEDI.
COREn
Synopsis:
COREn = BFXXX, [tap_num]
Description:
Type of CORE (BF50X, BF51X, BF522, BF525, BF527, BF531, BF532, BF533,
BF534, BF535, BF536, BF537, BF538, BF539, BF542, BF544, BF548, BF549,
BF561A, BF561B, BF59X, BF60X_A, BF60X_B, BF70X) and a TAP number
separated by comma
The following parameters are not mandatory. They are used to define a ’virtual’ memory region
corresponding to an external memory mapped device that is bigger than the visible external
asynchronous memory space. The higher address lines of the device that are not connected to the
CPU address buss must be driven by the GPIO pins. This way you can use all the PEEDI CLI
commands ( flash program , memory read , etc.) on the defined virtual region as the whole device is
directly visible in the memory space of the target. Actually PEEDI emulates this behavior by
accessing physically the device only through the memory window provided by the CPU external
address space and driving the higher address lines of the device depending on the address that is
requested to be accessed.
PEEDI User’s Manual
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