Using PEEDI
Description:
Address of the of pointer to the two page pointers array This parameter defines the
physical memory address, where PEEDI looks for the virtual address of the array with
the two page table pointers. If this configuration parameter is present and the MMU
translation is enabled, if PEEDI fails to translate the effective address to a physical one
using BAT translation, it tries a page translation. For more information see CPU
specific considerations.
Section PLATFORM_QorIQ_P
This section describes the QorIQ P3/4/5, T1/T2/4 cores connected to PEEDI.
COREn
Synopsis:
COREn = P4080A/B/C/D/E/F/G/H|T1040A/B/C/D|T2080/T4080,
<tap_num>
Description:
Type of CORE and a TAP number separated by comma
COREn_REGLIST
Synopsis:
COREn_REGLIST = 32BIT|64BIT
Description:
This parameter sets the type of the register frame sent to GDB, when debugging 64-bit
e5500/e6500 cores - 32 or 64 bit registers.
COREn_MMU_TRANS
Synopsis:
PEEDI User’s Manual
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