Using PEEDI
set cp15 0x51AF 0x123
; ARM9: set CP15 instr. TTB register using
interpreted access (bit12=1)
set cp15 0x000D 0x678
; ARM9: set CP15 Process ID register using
physical access (bit12=0)
set MAS0 0x1234
; PowerPC: set spr register by name
set spr 624 0x1234
; PowerPC: set spr register by number
set RAMBAR 0x0
; ColdFire: set control register by name
set ctrl 0xC05 0x0
; ColdFire: set control register by
address
set cp0 8 0x0
; MIPS: set control register by number
set tlb word0 word1 word2
; PPC4XX: set MMU TLB entry, the first
command used clears all TLB entries
halt
Syntax:
halt [#CORE|#all]
Description:
Stop current or specified core(s). If no core is specified, current will be stopped.
Argument:
#CORE
- core to be stop
#all
- all cores will be stopped
Example:
halt
halt #0
halt #all
reset
Syntax:
reset [detect|reset|run|stop [MILLISECONDS]]
Description:
Hardware reset all core on the JTAG chain causing re-initialization of each core.
PEEDI User’s Manual
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