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Ronetix PEEDI, User Manual

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Ronetix PEEDI User Manual Download Page 145

Using PEEDI

Secure AT91SAM7 CPU.

Argument:

Example:

flash this secure

flash this option

Syntax:

flash this option erase

flash this option BYTE VALUE

Description:

Manage ST STM32F1 CPU option bytes.

Argument:

BYTE

- byte number 0-7

VALUE

- value to be written to the option byte

Example:

flash this option 0x0FFFAAEC

flash this option

Syntax:

flash this OPTCR_VALUE

Description:

Manage ST STM32F2 CPU option bits.

Argument:

OPTCR_VALUE

- option bits value

Example:

PEEDI User’s Manual

145

www.ronetix.at

Summary of Contents for PEEDI

Page 1: ...PEEDI Powerful Embedded Ethernet Debug Interface User s Manual Version 3 0...

Page 2: ...s software on magnetic tape disk or other medium for any purpose other than the licensee s personal use Ronetix Development Tools GmbH Hirschstettner Str 19 Z110 1220 Vienna Austria Tel 43 1 236 1101...

Page 3: ...EEDI interface 18 3 2 Setup with RedBoot 19 3 2 1 RedBoot Configuration 20 3 3 Firmware update procedure 21 3 3 1 Update via RS232 22 3 3 2 Update via Ethernet 22 3 4 RedBoot commands used with PEEDI...

Page 4: ...n 41 COREn_USE_FAST_DOWNLOAD 41 COREn_DEBUG_HANDLER_ADDR 41 COREn_VECTOR RELOCATED_UNDEF SWI PABORT DABORT RES IRQ FIQ 42 Section PLATFORM_MPC5200 43 COREn 43 COREn_BOOT_ADDR 43 COREn_MEMDELAY 43 Sect...

Page 5: ...l AVR32UC3 programming 59 Freescale Kinetis programming 60 TI Luminary LM3S programming 60 NXP LPC2000 programming 60 Nordic Semiconductor nRF51 ans nRF52 programming 62 Freescale MAC7100 programming...

Page 6: ...L_DESCIPTOR_MAGIC 79 DAVINCI_UBL_DESCIPTOR_ENTRY_POINT 79 DAVINCI_UBL_DESCIPTOR_LOAD_ADDR 80 DAVINCI_UBL_MAX_IMAGE_SIZE 80 NUM_ECC 80 HEADER 80 IPS_BASE 81 SPIFI_BASE 81 NCB_DATA 81 LDLB_DATA 81 SERIA...

Page 7: ...thread awareness 102 3 15 Working with CLI Command Line Interface 105 3 15 1 File path convention 106 3 15 2 CLI commands 108 help 108 transfer 109 type 109 wait 110 core 110 clock 111 run 111 go 112...

Page 8: ...42 flash area 143 flash this 144 flash this hidden 144 flash this markbad 145 flash this nvmbit 145 flash this secure 145 flash this option 146 flash this option 146 flash this write 147 flash this pa...

Page 9: ...61 amp 162 3 15 3 Working with the FLASH programmer 162 3 16 Multiple FLASH support 164 3 17 Working with a MMC SD memory card 164 3 18 JTAG cable adapters 165 3 19 PEEDI licenses 166 4 Specifications...

Page 10: ...Panel 16 Figure 2 2 PEEDI Rear Panel 16 Figure 2 3 Direct host connection 17 Figure 2 4 LAN connection 17 Figure 2 5 Target connection 17 Figure 3 1 Front panel interface 18 Figure 3 2 Rear panel inte...

Page 11: ...see what is taking place in the target system and control its behavior PEEDI provides the services needed to perform all debugging operations It receives command packets over the communication link a...

Page 12: ...loper s PC as a host computer this is suitable for small projects Here all necessary tools for compiling and debugging the project must be installed on the developers PC including file server TFTP FTP...

Page 13: ...l Source Safe can be used for synchronizing the project files In this configuration Figure 2 all devices the server the developers PCs and all PEEDIs must be connected in a common LAN Figure 1 2 Multi...

Page 14: ...and errors and therefore maybe the preferred method Figure 1 3 FLASH programmer with PC The second way Figure 1 4 FLASH programmer without PC is to use the front panel interface to choose start and ob...

Page 15: ...e 1 2 3 High productivity with the Multi Program feature With the Multi Program feature users can increase productivity by working on upto four boards simultaneously using a single PEEDI The boards mu...

Page 16: ...START SELECT TARGET Figure 2 1 PEEDI Front Panel RS232 port Power connector Ethernet port RS232 5V 1A RST Ethernet Figure 2 2 PEEDI Rear Panel 2 1 1 Connection instructions To connect the PEEDI interf...

Page 17: ...cable If your target JTAG port pinout is not standard you may need to make your own target cable considering the PEEDI JTAG connector pinout Refer to subsection 4 1 JTAG Target connector signals for t...

Page 18: ...ains arm arm_cross_development_guide pdf 3 Using PEEDI This chapter will explain PEEDI s operating modes PEEDI s interface and the basic steps of configuring the software tools for working with PEEDI...

Page 19: ...cript number status LED display 6 Next script button 7 Start script button 8 Target connector 9 MMC SD card slot 10 RS232 port 11 Power supply 12 Reset button 13 Ethernet port 3 2 Setup with RedBoot R...

Page 20: ...on the serial port which you should see When RedBoot is ready to accept commands it will show the command line prompt RedBoot Now you can use the fconfig command to set and save to FLASH all the para...

Page 21: ...port RedBoot telnet port 23 Finally you may enter the update command default file path Update filepath 1 http www ronetix at download firmware fw_peedi_revA_last bin 2 tftp 192 168 3 1 fw_peedi_rev A_...

Page 22: ...update xmodem or RedBoot update ymodem to tell RedBoot to start listening on RS232 port for incoming packets Next tell your terminal application to start downloading the PEEDI firmware 3 3 2 Update vi...

Page 23: ...ttp server subdir file bin RedBoot newer than v20 11 4 accept also RedBoot update file bin In this case the command will be expanded to RedBoot update tftp server_ip file bin where server_ip is define...

Page 24: ...Program from 0x007f0000 0x00800000 at 0x019f0000 fis create b 0x100000 l 0x1AB1C0 f 0x1840000 e 0x600040 r 0x600000 peedi Erase from 0x01840000 0x019f0000 Program from 0x00100000 0x002ab1c0 at 0x01840...

Page 25: ...ate 1 update file bin expanded to tftp server_ip file bin config Syntax config file cfg Description Set target configuration file Argument FILEPATH file path of the file FILE filename which will be ex...

Page 26: ...n file To operate PEEDI needs to load a target configuration file which describes the specifics of the given target this includes CPU type FLASH type and metrics RAM address and size etc The target co...

Page 27: ...icenses txt In this case the file licenses txt should contains LICENSE KEY ARM7_ARM9 1111 2222 3333 4 KEY UPDATE_29AUG2006 5555 6666 7777 8 Section DEBUGGER This section describes the protocol used wi...

Page 28: ...LASH section to be used for core 0 FLASH0 FLASH_NAND FLASH section to be used for core 0 FLASH1 FLASH_NAND FLASH section to be used for core 1 Section TARGET This section describes the target s platfo...

Page 29: ...rameters see below If AUTO X is used first then PEEDI will try to auto detect the actual number of TAPs connected in the JTAG chain Example JTAG_CHAIN 4 4 6 JTAG_CHAIN AUTO x 5 4 JTAG_TDO_DELAY Synops...

Page 30: ...also be missing If the target executes code after reset even CORE_STARTUP_MODE RESET this means the TAP is not active during reset Example RESET_TIME 20 RESET_TYPE Synopsis RESET_TYPE ICEPICK C ICEPI...

Page 31: ...AG operations after RESET is released DBGREQ_OUTPUT Synopsis DBGREQ_OUTPUT HIGH LOW Description Define the state of the JTAG DBGREQ line COREn Synopsis COREn CORE_TYPE tap_num Description Type of CORE...

Page 32: ...tion Section to be executed in order to initialize the target COREn_FLASHm Synopsis COREn_FLASHm flash_section Description This parameter points a section which contains the target FLASH description I...

Page 33: ...itions never mind break or watch points The use of software breakpoints allows unlimited number of them but this still requires the hardware resource of one break watch point Software breakpoints are...

Page 34: ...use the workspace for storing only the agent code and the dataspace for the agent data This is useful when using internal RAM for agent programming where the internal RAM is code or data only for exa...

Page 35: ...n_LOCKOUT_RECOVERY value Firmware after v20 12 xx COREn_LOCKOUT_RECOVERY LM3S KINETIS NRF52 COREn_LOCKOUT_RECOVERY MAC7100_4MHz MAC7100_8MHz COREn_LOCKOUT_RECOVERY YES NO Description If this parameter...

Page 36: ...n the target OS tasks and pass the list to the host debugger Section PLATFORM_ARM and PLATFORM_ARM11 COREn Synopsis COREn ARM7TDMI ARM9TDMI ARM920T ARM940T ARM926E ARM946E tap_num COREn ARM1136 ARM115...

Page 37: ...oute 4 virtual serial ports to TCP ports 2001 2004 COREn_USE_FAST_DOWNLOAD Synopsis COREn_USE_FAST_DOWNLOAD YES NO Description Only by PLATFORM_ARM11 TCP port the target s DCC channel to be routed to...

Page 38: ...e same format as the JTAG_CLOCK parameter About the CORE parameter COREn Synopsis COREn Cortex M Cortex A Cortex ARMv8 tap_num tap_id COREn Cortex A_SMP COREn Cortex A_AMP Description The detection of...

Page 39: ...er components Example COREn_DEBUG_ADDR 0x80070000 0x80078000 COREn_DEBUG_ADDR 0x80070000 COREn_DAPPC Synopsis COREn_DAPPC address Description This parameter is necessary for some TI processors OMAP3 O...

Page 40: ...to that TCP port PEEDI will forward all stimulus data for the given stimulus channel In order for the CPU to transmit stimulus messages you need to enable this functionality This can be done by the ta...

Page 41: ...e cores connected to PEEDI COREn Synopsis COREn XScale PXA320 tap_num Description Type of CORE and a TAP number separated by comma COREn_USE_FAST_DOWNLOAD Synopsis COREn_USE_FAST_DOWNLOAD YES NO Descr...

Page 42: ...nstr_code COREn_VECTOR_RES AUTO instr_code COREn_VECTOR_IRQ AUTO instr_code COREn_VECTOR_FIQ AUTO instr_code COREn_RELOCATED_UNDEF AUTO instr_code COREn_RELOCATED_SWI AUTO instr_code COREn_RELOCATED_P...

Page 43: ...ption Type of CORE and a TAP number separated by comma COREn_BOOT_ADDR Synopsis COREn_BOOT_ADDR 0x00000100 0xFFF00100 Description Normally the boot address for PowerPC is 0xFFF00100 or 0x00000100 depe...

Page 44: ...region is supplied usually this is the RAM of the target PEEDI will access target memory region using the nexus3 module This method is about three times faster but it uses physical addresses i e bypas...

Page 45: ...COREn_BOOT_ADDR 0x00000100 0xFFF00100 Description Normally the boot address for PowerPC is 0xFFF00100 or 0x00000100 depending on the Reset Configuration Word RCW PEEDI sets a hardware breakpoint at t...

Page 46: ...slation it tries a page translation For more information see CPU specific considerations Section PLATFORM_MPC8500 This section describes the MPC8500 cores connected to PEEDI COREn Synopsis COREn MPC85...

Page 47: ...translation it tries a page translation For more information see CPU specific considerations Section PLATFORM_QorIQ_P This section describes the QorIQ P3 4 5 T1 T2 4 cores connected to PEEDI COREn Syn...

Page 48: ...to a physical one using BAT translation it tries a page translation For more information see CPU specific considerations COREn_PMEM_BASE Synopsis COREn_PMEM_BASE addr Description Address of the of poi...

Page 49: ...fore and after initialization MAX BDM clock is 33MHz See your ColdFire CPU user s manual for correct BDM clock Use ADAPTIVE_n to set the BDM clock to PSTCLK n CORE Synopsis CORE MCFxxxx Description Ty...

Page 50: ...BF532 BF533 BF534 BF535 BF536 BF537 BF538 BF539 BF542 BF544 BF548 BF549 BF561A BF561B BF59X BF60X_A BF60X_B BF70X and a TAP number separated by comma The following parameters are not mandatory They a...

Page 51: ...memory space COREn_VMEM_PINS Synopsis COREn_VMEM_PINS P A J 0 15 Description Pxy where x is the GPIO port A J and y is the bit number 0 15 List of the GPIO pins connected to the higher external devic...

Page 52: ...P start_addr end_addr Description Defines a valid memory region Up to 32 regions can be defined in the target configuration file When even one region is defined PEEDI begins to check every memory acce...

Page 53: ...rt address and length in bytes If a memory region is supplied usually this is the RAM of the target PEEDI will access target memory region using the MEMORY_WORD_ACCESS TAP command Section INIT This is...

Page 54: ...sful initialization Note This is working INIT section for AT91M55800A CPU In this case the last instruction of the executable must be SWI informing that job has finished INIT_EB55800 First init chip s...

Page 55: ...he following parameters have to be specified CHIP CHECK_ID ACCESS_METHOD CHIP_WIDTH CHIP_COUNT BASE_ADDR FILE AUTO_ERASE AUTO_LOCK Considering your configuration you must specify CHIP_COUNT and CHIP_W...

Page 56: ...IP_SIZE I2C_ADDR I2C_DELAY SDA_SET CLR SDA_IN OUT SDA_READ SCL_SET CLR FILE AUTO_ERASE Example http download ronetix at peedi cfg_examples arm11 s3c6410 cfg SPI FLASH programming The parameters for SP...

Page 57: ...RASE Example http download ronetix at peedi cfg_examples arm9 at91sam9263_soft_spi cfg NAND FLASH programming PEEDI is able to program all NAND chips with 8 and 16 bits data bus The INIT section of th...

Page 58: ...For this the OOB_INFO parameter must be set to JFFS2 This way PEEDI will the write the data loading from the image file and will calculate the ECC and program it to the OBB spare bytes PEEDI supports...

Page 59: ...edi cfg_examples blackfin bf527 cfg OneNAND FLASH programming Example http download ronetix at peedi cfg_examples xscale pxa270_onenand cfg MMC SD card programming The parameters for MMC SD card are C...

Page 60: ...sue the previous command every time you need to verify or you may put it in the init section of the core in the target configuration file this way it will be executed automatically To secure the LPC20...

Page 61: ...LPC54100 For example to enable flash programming for LPC1343 do CHIP LPC1100 Supported devices for CHIP LPC800 LPC810 LPC811 LPC812 LPC822 LPC824 Supported devices for CHIP LPC1100 LPC1110 LPC1111 LPC...

Page 62: ...are specified by there chipname Supported devices for CHIP LPC2900 family This family of LPC CPU s is a different group because its flash algorithms for programming vary from the other groups Example...

Page 63: ...cure the FLASH incidentally so avoid placing code there flash erase chip perform MASS ERASE flash lock write at address 0xFC100414 0xFFFFFFFC0 enable flash security If the Flash security is enabled th...

Page 64: ...this will erase all other option values so you may need to set them again Example http download ronetix at peedi cfg_examples cortex m stm32 cfg ST STR7 programming In the STR7 microcontrollers severa...

Page 65: ...edi cfg_examples arm9 str9 cfg TI TMS570 programming Example http download ronetix at peedi cfg_examples cortex a tms570 cfg TI TMS470 programming TMS470 devices use four WORD long keys to protect FLA...

Page 66: ...e it has been partly secured The ALLOW_ZERO_KEYS FLASH section parameter is used to protect the device from unwanted permanent locking of the device this may happen if MSM keys all of 0x000000000 are...

Page 67: ...d FLASH ID and will find the right chip among the all chips enumerated using the CHIP parameter CHECK_ID Synopsis CHECK_ID YES NO Description When specified YES if single FLASH chip is described by th...

Page 68: ...re the first bank of a device with flash banks A and B specify the parameter like so BANK 0 To configure the second bank specify BANK 1 ACCESS_METHOD Synopsis ACCESS_METHOD AUTO AGENT DIRECT Descripti...

Page 69: ...eral widths CHIP_COUNT Synopsis CHIP_COUNT 1 2 4 Description Number of FLASH chips CHIP_SIZE Synopsis CHIP_SIZE chip_size page_size Description Size of EEPROM chip and optional write page size BASE_AD...

Page 70: ...iles and optional for all other types of files it is the address where the file should be loaded SPI_MODE Synopsis SPI_MODE number Description By default this parameter takes the value of 0 Available...

Page 71: ...FLASH is erased so any JTAG operations are impossible after FLASH is programmed and secured Used when describing internal FLASH of Atmel AT91SAM7 series microcontrollers SET_VECTORS_CHECKSUM Synopsis...

Page 72: ...to the sizes of the STR9 FLASH banks Used when describing internal FLASH of ST STR9 series microcontrollers F2F4_PSIZE Synopsis F2F4_PSIZE 8 16 32 64 Description Set this parameter 8 16 32 or 64 which...

Page 73: ...of new Memory Security Module keys that are all 0x00000000 because this will permanently lock the TMS against debugging and programming Used when describing internal FLASH of TI TMS470 series microcon...

Page 74: ...IV Used when describing SPI Flash nSPI Synopsis nSPI 0 1 Description SPI controller to use Used when describing SPI Flash nCS Synopsis nCS 0 3 Description Chip select to use Used when describing SPI F...

Page 75: ...ess Description Base address that if written to the NAND CLE signal will be asserted On MPC83XX devices with built in NAND FLASH controller this parameter tells PEEDI the offset of Internal Memory Map...

Page 76: ...SE address data Description Describes memory write operation address data that will assert release the NAND chip select Address Latch Enable and Command Latch Enable connected to a corresponding PIO p...

Page 77: ...s SWAP_BI YES NO Description If this parameter is set to YES PEEDI will swap the bad block marker ECC byte with a spare one This option is applicable for iMX21 iMX25 iMX27 iMX31 and iMX35 targets only...

Page 78: ...ECC IMX23_BCH Freescale iMX23 hardware ECC LPC_ECC NXP LPC hardware ECC OMAP3_ECC TI Omap3 hardware ECC OMAP4_BCH8_ROMCODE TI Omap4 hardware ECC OMAP4_BCH8 TI Omap4 hardware ECC OMAP4_HAMMING TI Omap4...

Page 79: ...AVINCI_UBL_DESCIPTOR_MAGIC Synopsis DAVINCI_UBL_DESCIPTOR_MAGIC value Description Descriptor magic the first 32 bit value in the UBL descriptor It set to non zero value programming of the file image i...

Page 80: ...Value Description Used by PEEDI to print a warning if the programmed file size exceeds this limit Used when describing NAND FLASH for TI DaVinci CPU NUM_ECC Synopsis NUM_ECC Value Description Set the...

Page 81: ...I_BASE Synopsis SPIFI_BASE address Description NXP SPIFI controller base address NCB_DATA Synopsis NCB_DATA value0 value1 Description Freescale iMX23 NCB data structure to be programmed in NAND LDLB_D...

Page 82: ...341 end of file Each time PEEDI programs a board it loads the file gets the last serial number increments it and stores the new value back in the file and so if the file resides on a TFTP or a FTP ser...

Page 83: ...rmitted AND The value pointed by the address is AND ed with the given data OR The value pointed by the address is OR ed with the given data EQU The data provided is written at the given address CS_ASS...

Page 84: ...it access type_access argument might has a _abs suffix which means that the address calculated of the offset parameters is an absolute memory location not an offset from the base of the task name name...

Page 85: ...abs BASE 0x20000000 0x1234 offset2 ITEM int32 PID 0xA4 PID BASE 0xA4 ITEM string NAME 0xEC offset2 offset3 ITEM int32 R0 0xC R0 BASE 0xC ITEM int32 R1 0x10 0x20 R1 BASE 0x10 0x20 ITEM reg32_abs xPSR 0...

Page 86: ...BAUD 115200 STOP_BITS 1 PARITY NONE TCP_PORT 2023 Section TELNET This section has only two parameters The first sets the new command prompt string after the configuration file is loaded The second pa...

Page 87: ...VOLUME 100 enable beeper Section ACTIONS Declares what scripts can be executed using front panel buttons each declaration must be on a new line The declaration consists of a number associated with the...

Page 88: ...argument of the JTAG_CLOCK parameter 3 6 2 ST STM32 family Use the following commands in the target INIT script to enable SWO stimulus output init SWO mem wr 0xE0042004 0x20 TRACE_IOEN async mode mem...

Page 89: ...debug event you can again start it and the exception vectors will be updated You can use the first way and a wait command to automate this in the INIT section of the target configuration file INIT_XSC...

Page 90: ...the debug info because of an internal bug in this case adding gstabs option in the makefile fixes this WARNING On some cores MPC8349 in order the software breakpoints to work the interrupt vectors mu...

Page 91: ...presence of the ADI USB JTAG debug interface BF535 Spartan FPGA interferes the normal PEEDI operation seen with some EZ KIT and STAMP boards Some Blackfin boards do not work reliably with low JTAG cl...

Page 92: ...rget RST Wait TIME_AFETER_RESET Set initial JTAG_CLOCK read CPU ID and check EmbeddedICE logic COREn_STARTUP_MODE RUN COREn_STARTUP_MODE STOP period Wait specified period Stop target CPU and read all...

Page 93: ...power supply 10 tolerance is permissible The highest power supply is taken for reference for the PEEDI output schematic so the JTAG signals will have that value WARNING As short as possible cables sh...

Page 94: ...programming CORE1_PATH tftp 192 168 3 1 CORE2 Cortex M 5 TAP is CortexM3 CPU CORE2_STARTUP_MODE RESET stop the core immediately after reset CORE2_ENDIAN LITTLE core is little endian CORE2_BREAKMODE H...

Page 95: ...el buttons Press the green button to choose the script you wish to execute the LED indicator will show the numbers associated with the available scripts when ready with the choice press the red button...

Page 96: ...ed script_name and put any number of commands each command must be on a new line These scripts are useful when using PEEDI in autonomous stand alone mode not connected to a PC In such mode PEEDI can b...

Page 97: ...edefined TCP port in the configuration file This way if a telnet connection is opened to that TCP port the telnet application will receive each byte coming in through the RS232 port Vice versa all dat...

Page 98: ...14 0 0 c0 c0 n r status while status DCC_TX_BUSY __asm__ mcr p14 0 0 c1 c0 n r cc void dcc_send_string const char ss while ss dcc_send_char ss Keep in mind that these are blocking functions 3 12 Worki...

Page 99: ...t files While load command is being executed gdb sets PC to the entry point of the application If you want to start execution from another point or just the real entry point is different from the one...

Page 100: ...d my_gdb_init Assuming that PEEDI has IP 192 168 1 10 my_gdb_init file may contain something like this this will tell gdb to connect to PEEDI using remote protocol target remote 192 168 1 10 2000 info...

Page 101: ...ire If a break point is hit gdb insight will highlight the source line where the execution has stopped 3 14 Target OS thread awareness PEEDI provides target OS thread awareness for systems that suppor...

Page 102: ...itialized memory for example after the first si command it is recommended gdbinit file to clear the first NEXT pointer Something like this set Cyg_Thread thread_list next 0 Start your project with GDB...

Page 103: ...C 0xC ITEM reg32 R1 0xC 0x10 ITEM reg32 R2 0xC 0x14 ITEM reg32 R3 0xC 0x18 ITEM reg32 R4 0xC 0x1C ITEM reg32 R5 0xC 0x20 ITEM reg32 R6 0xC 0x24 ITEM reg32 R7 0xC 0x28 ITEM reg32 R8 0xC 0x2C ITEM reg32...

Page 104: ...I CLI allows you to Perform simple debugging You can load executable image into target RAM get or set target memory or registers put break and watch points start step or stop the target For more infor...

Page 105: ...nfiguration file using the COREn_PATH parameter Full path will be used in the entire manual for clear understanding Note If the IP address is skipped the default server IP will be used The default ser...

Page 106: ...om server root directory using user and password credentials to login ftp user password subdirectory file FTP default server IP will be requested for subdirectory file from server root directory using...

Page 107: ...es many useful commands It has vary easy to use help system and command auto complete so instead of flash program you could type only fl pr or you could just hit TAB to auto complete the command or su...

Page 108: ...PROM Argument SOURCE the source file to be copied DESTINATION where the file to be saved Example copy file from the mmc sd card to a TFTP server transfer card dump bin tftp 192 168 1 1 dump bin copy f...

Page 109: ...cified time period or wait target to stop with a given timeout Useful when target needs some delay while executing commands in INIT section of the target configuration or script file Argument MILLISEC...

Page 110: ...s too much time Using this command you can initialize in the beginning the system clock the PLL and then switch to normal clock This will allow much faster execution of the INIT section Argument init...

Page 111: ...ESS all Description Start current or specified core s If no address is provided the core s will start from its current program counter PC value If no core is specified current core will be started If...

Page 112: ...00 step Syntax step ADDRESS CORE CORE ADDRESS all Description Step one instruction current or specified core s If no address is provided the core s will steps from its current PC value If no core is s...

Page 113: ...ple execute 0x7C0007A4 set Syntax set coprocessor spr ctrl cp0 tlb REGISTER VALUE Description Set target CPU register For more information about cp15 see info cp15 command Argument REGISTER name of re...

Page 114: ...et control register by address set cp0 8 0x0 MIPS set control register by number set tlb word0 word1 word2 PPC4XX set MMU TLB entry the first command used clears all TLB entries halt Syntax halt CORE...

Page 115: ...nd stop the target after specified time detect 0 disable the target reset detection detect 1 enable the target reset detection Example reset reset run reset stop 1000 reset detect 0 reset detect 1 reb...

Page 116: ...mand line watchdog Enable PEEDI internal watchdog Example echo Initializing SDRAM jtag Syntax jtag Description Type jtag help in PEEDI command line for more information beep Syntax beep FREQUENCY DURA...

Page 117: ...detach attach Description Set PEEDI debug interface in High Z state Argument attach detach Example target show current interface state target detach set interface in High Z target attach set interfac...

Page 118: ...about specified topic Argument SUBCOMMAND sub command specifying the needed information Example info config Info flash Syntax info flash Description Show target FLASH configuration information Argumen...

Page 119: ...list all core registers values all list all modes registers values Example info registers info registers all info registers 0 info registers 0 all info registers all info registers all all info targe...

Page 120: ...ion Display ARM ICE Breaker registers Argument Example info ice info ice ice5 info ice 5 info cp15 info cp14 Syntax info cp15 0xXXXX CORE all info cp14 0xXXXX CORE all Description List current CP15 re...

Page 121: ...for interpreted access mode bit 12 1 15 13 12 11 8 7 5 4 3 0 opc_2 1 CRm opc_2 x CRn The 16 bit register number is used to build the appropriate MCR MRC instruction CRm Specified Coprocessor Action De...

Page 122: ...show inst TTB register using interpreted access bit12 1 info cp15 0x0109 ARM920 show inst cache lockdown register using physical access bit12 0 info cp15 ittb info spr Syntax info spr NAME NUMBER CORE...

Page 123: ...point Syntax info breakpoint CORE Description List all set break and watch points of current or a specified core Argument CORE core s break and watch points to be listed Example info breakpoint info b...

Page 124: ...ad Default first used arguments are 8 32 bit values at address 0x00000000 Argument TYPE memory access 8 value is 8 bits byte long 16 value is 16 bits half word long 32 value is 32 bits word long 64 va...

Page 125: ...ere the value is to be written COUNT how many consecutive values to be written if not provided count 1 is assumed Example memory write 0x1000 0x5555AAAA memory write8 0x1000 0x5A memory write16 0x1000...

Page 126: ...00 0x1234567811223344 memory and Syntax memory and TYPE ADDRESS MASK Description Make logical AND with and apply to target memory Argument TYPE memory access 8 value is 8 bits byte long 16 value is 16...

Page 127: ...00000 1024 0x1DF37A8C memory load Syntax memory load FILE FORMAT OFFSET Description Load image file into target memory If no arguments are provided last used will be taken Default first used arguments...

Page 128: ...targets simultaneously If no arguments are provided last used will be taken Default first used arguments are taken from COREn_FILE of target configuration file While file is loaded PC will be set at s...

Page 129: ...FILE the image file to be verified FORMAT format of image file bin binary file ihex Intel HEX format srec Motorola S record format elf ELF format OFFSET Must be provided for binary files because they...

Page 130: ...r read TLB entries tlbw write TLB entries tlbc clear TLB entries Example Example PPC440 memory management tlbr START_TLB_INDEX END_TLB_INDEX memory management tlbw TLB_INDEX WS0_WORD WS1_WORD WS2_WORD...

Page 131: ...RESS beginning of memory region LENGTH length of memory region STEP incrementing address step COUNT number of incrementing steps Example memory test 0x100000 1024 Test first 32 bytes of every 8KB from...

Page 132: ...blank Syntax flash blank ADDRESS LENGTH Description Check FLASH region if it is blank i e filled with 0xFF If no arguments are provided last used will be taken Default first used region is whole FLAS...

Page 133: ...egion LENGTH length of FLASH region default is 1 if not supplied Example flash erase 0x400000 0x1000 flash erase chip flash lock Syntax flash lock ADDRESS LENGTH Description If supported by FLASH lock...

Page 134: ...H region default is 1 if not supplied Example flash unlock 0x400000 0x1000 flash query Syntax flash query ADDRESS LENGTH Description If supported by FLASH show the lock status of all FLASH sectors tha...

Page 135: ...file ihex Intel HEX format srec Motorola S record format elf ELF format OFFSET Must be provided for binary files because they don t have any address information If provided with ihex srec or elf forma...

Page 136: ...not supplied Example flash multi erase all 0x400000 0x1000 flash multi erase 1 2 0x400000 0x1000 flash multi erase all chip flash multi blank Syntax flash multi blank CORE0 COREn ADDRESS LENGTH Descri...

Page 137: ...ction in target configuration file Argument CORE0 COREn or all cores to program FILE the image file to be programmed FORMAT format of image file bin binary file ihex Intel HEX format srec Motorola S r...

Page 138: ...se they don t have any address information If provided with ihex srec or elf formats all the code will be shifted regarding the specified offset Example flash verify tftp 192 168 1 1 image elf elf fla...

Page 139: ...f formats all the code will be shifted regarding the specified offset Example flash multi verify all tftp 192 168 1 1 image elf elf flash multi verify 0 2 ftp 192 168 1 1 image bin bin 0x100 flash dum...

Page 140: ...taFlash FLASH types i e chips which are not visible through the CPU memory map For NOR chips the memory read command may be used Argument ADDRESS start address COUNT count in bytes Example flash read...

Page 141: ...ENGTH Description On NAND Flash devices the whole NAND Flash is erased and then the given region is programmed and verified the with two patterns At the end the whole device is erased The already exis...

Page 142: ...egion is programmed and verified the with two patterns At the end the whole device is erased The already existing bad blocks will be skipped but the tested area will be not expanded The new detected b...

Page 143: ...t BIT VALUE flash this secure flash this option BYTE VALUE flash this write ADDRESS VALUE1 VALUE14 flash this hidden Syntax flash this hidden enter exit Description Enter exit hidden ROM mode on some...

Page 144: ...lash this markbad 5 flash this markbad 13 123 1365 flash this nvmbit Syntax flash this nvmbit BIT VALUE Description Set clear Atmel AT91SAM7 general purpose NVM bit Argument BIT bit number VALUE 0 to...

Page 145: ...UE Description Manage ST STM32F1 CPU option bytes Argument BYTE byte number 0 7 VALUE value to be written to the option byte Example flash this option 0x0FFFAAEC flash this option Syntax flash this OP...

Page 146: ...ite flash this part Syntax flash this part VALUE Description Used to program eMMC register PARTITION_CONFIG 179 Argument VALUE register value Example flash this part 0x48 program partition configurati...

Page 147: ...s used to execute FLASH reading or writing of protected registers only for the Intel Strata NOR flash See below for the available commands Argument SUBCOMMAND FLASH specific subcommand to be executed...

Page 148: ...ecute FLASH writing of protected registers only for the Intel Strata NOR flash See below for the available commands Argument ADDRESS Flash address to be programmed COUNT The value to be programmed Exa...

Page 149: ...erase command is used to erase STR9 ISC Argument SECTOR_BITMASK Example flash this isc_erase ISC full erase flash this isc_erase 0x3 ISC erase sector 0 and 1 of bank 0 flash this isc_conf_write Syntax...

Page 150: ...this isc_conf_boot_bank Syntax flash this isc_conf_boot_bank BANK Description The flash this isc_conf_boot_bank command is used to set the STR9 device boot bank Argument BANK bank to boot from Example...

Page 151: ...t list breakpoint add Syntax breakpoint add hard watch ADDRESS ACCESS TYPE Description Set software break point Unlimited number of software break points can be set If address 1 or 0xFFFFFFFF is speci...

Page 152: ...atched value 8 value is 8 bit byte 16 value is 16 bit half word 32 value is 32 bit word Example breakpoint add watch 0x400040 32 r breakpoint list Syntax breakpoint list CORE Description List all set...

Page 153: ...ed taken using breakpoint list command all if provided all break and watch points will be deleted Example breakpoint delete 7 breakpoint delete all card Syntax card SUBCOMMAND Description Manage MMC S...

Page 154: ...d rd DIRECTORY Description Remove directory The directory must be empty Argument DIRECTORY directory to be removed Example card rd mydir card dir Syntax card dir SEARCHCRITERIA DIRECTORY Description D...

Page 155: ...OURCE DESTINATION Description Copy file Argument SOURCE the source file to be copied DESTINATION file to be saved Example card copy image bin mydir backup bin card type Syntax card type FILE Descripti...

Page 156: ...ment FILE file to be deleted Example card delete target cfg card rename Syntax card rename FILE NEWNAME Description Rename file Argument FILE file to be renamed NEWNAME new file name Example card rena...

Page 157: ...es Subcommand must be provided Argument SUBCOMMAND subcommand specifying the operation Example eeprom dir eeprom dir Syntax eeprom dir SEARCHCRITERIA Description Displays a list of files Argument SEAR...

Page 158: ...ckup cfg eeprom type Syntax eeprom type FILE Description Show content of text file Argument FILE text file to be shown Example eeprom type target cfg eeprom delete Syntax eeprom delete FILE Descriptio...

Page 159: ...LE file to be renamed NEWNAME new file name Example eeprom rename image bin backup bin eeprom format Syntax eeprom format Description Format EEPROM file system erasing all files Argument Example eepro...

Page 160: ...mory calculate the crc32 checksum and compare it with the given CRC32 After every test loop the number of the loops and errors are printed Argument FILE file to be loaded only BIN format is supported...

Page 161: ...t memory is used but very slow 2 Using small agent program which is downloaded to the target RAM 1KB and uses configurable data buffer 0 5 64KB So you can choose which is best suitable for your needs...

Page 162: ...e peedi flash program tftp 192 168 1 1 mydir myimage bin bin 0x100 The address to program the image at must be aligned to the FLASH access width i e if the FLASH is 16 bits 2 bytes accessible the addr...

Page 163: ...ultiple FLASH support could also be used to describe different profiles for the same FLASH for example with different program method type or different image file specified This way you can easy switch...

Page 164: ...to a target system There are several target adapters available upon request 10 pin for Cortex targets 14 pin for MIPS 32 TI OMAP Freescale PowerPC MPC5500 and Analog Devices Blackfin targets 16 pin f...

Page 165: ...red licenses are provided when PEEDI is purchased and are printed on the bottom side of PEEDI Also new units are set to load the target configuration file from the EEPROM where we have put the file an...

Page 166: ...everse polarity protection over voltage protection up to 100V 6 9V over voltage shutdown Robust Aluminum case Dimensions 115x105x35mm Weight 270 gram LEDs Power Red Target Power Red Ethernet Status Or...

Page 167: ...gic levels to the target It is normally fed from Vcc I O on the target board 2 GND 3 TCK Output JTAG Clock Connects to the target TCK line 4 GND 5 TDI Output JTAG TDI Test Data In signal from PEEDI to...

Page 168: ...TAG Reset Resets the JTAG TAP controller on the target Driver type is specified in config file 20 RST Open Drain RESET Resets the target system Note Each signal JTAG pin has a 10k pull up 4 2 RS232 Co...

Page 169: ...d to implied warranties of merchantability and fitness for particular purposes with respect to defects in PEEDI and the program license granted herein including without limitation the operation of the...

Page 170: ...ic to the ARM microcontroller which can be accessed externally through a JTAG port Hence software debug is facilitated by interfacing these JTAG pins of the micro to the host development system contai...

Page 171: ...ll functions and look at system registers Besides all these fun things a debugger can be used to fix your programs Q How to set gdb to work with PEEDI A First compiled your application with the g O0 o...

Page 172: ...dow System to the Microsoft Windows family of operating systems Cygwin X runs on all recent consumer and business versions of Windows as of 2003 12 27 those versions are specifically Windows 95 Window...

Page 173: ...w_target_cfg_file_path Q How to set the network configuration of PEEDI A Enter RedBoot command line and use fconfig command Q Why PEEDI has a display and two buttons on the front panel A These are use...

Page 174: ...p download ronetix at peedi cfg_examples 8 Glossary A Alias User defined alias of a command including its arguments Agent Small program downloaded into the target which is used for faster operations B...

Page 175: ...ding debugging services to a target being debugged Hardware breakpoint I Insight Graphical User Interface of GDB Image An executable file that has been loaded onto a processor for execution J JTAG Typ...

Page 176: ...ion parameters or to load and launch the PEEDI executable image S Script List of CLI commands executed one by one until the last or until an error is returned T Target configuration file File used to...

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