Remote Control Basics
R&S
®
NRX
464
User Manual 1178.5566.02 ─ 07
Sum bit
The sum bit is obtained from the
EVENt
and
ENABle
part for each register. The result
is then entered into a bit of the
CONDition
part of the higher-order register.
The instrument automatically generates the sum bit for each register. Thus an event
can lead to a service request throughout all levels of the hierarchy.
14.4.3
Status Byte (STB) and Service Request Enable Register (SRE)
The status byte register is already defined in IEEE 488.2. It gives a rough overview of
the instrument status, collecting information from the lower-level registers. It is compa-
rable with the
CONDition
register of a SCPI defined register and is at the highest level
of the SCPI hierarchy. Its special feature is that bit 6 acts as the summary bit of all
other bits of the status byte register.
The status byte register is read by
or a serial poll. The service request enable
register is associated with the status byte register. The function of the service request
enable register corresponds to that of the
ENABle
register of the SCPI registers. Each
bit of the status byte register is assigned a bit in the service request enable register.
Bit
6 of the service request enable register is ignored. If a bit is set in the service
request enable register and the associated bit in the status byte register changes from
0 to 1, a service request (SRQ) is generated on the IEC/IEEE bus. This service request
triggers an interrupt in the controller configured for this purpose, and can be further
processed by the controller.
Set and read the service request enable register using
.
See
.
Table 14-4: Used status byte bits and their meaning
Bit
no.
Short description
Bit is set if
1
Device status register summary
A instrument is connected or disconnected or when an error
has occurred in a instrument, depending on the configuration
of the instrument status register.
Chapter 14.4.5, "Device Status Register"
2
Error queue not empty
The error queue has an entry. If this bit is enabled by the ser-
vice request enable register, each entry of the error queue
generates a service request. An error can thus be recognized
and specified in detail by querying the error queue. The query
yields a conclusive error message. This procedure is recom-
mended since it considerably reduces the problems of IEC/
IEEE-bus control.
3
Questionable status register
summary
An
EVENt
bit is set in the
QUEStionable
status register and
the associated
ENABLe
bit is set to 1. A set bit denotes a ques-
tionable device status which can be specified in greater detail
by querying the questionable status register.
Chapter 14.4.6, "Questionable Status Register"
4
MAV
Message available
A readable message is in the output queue. This bit can be
used to automate reading of data from the instrument into the
controller.
Status Reporting System
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