RANA Systems Elite Controller, User Manual

Page: 175 / 328

ELITE SERIES USER MANUAL THEORY OF OPERATION
7.2.6. Addressable Latch
The addressable latch is used to store the oper—
ating mode of the controller including the se-
lected disk drive, the phase of the stepper
motor, the motor enable state, and the function
currently being performed.
7 . 2 . 7 . A l t e r n a t e P a i r S e l e c t L o g i c
Selection of the second pair of disk drives is
accomplished by detecting a write to the periph-
eral expansion area which normally contains ROM.
The controller will only recognize the write if
its own EPROM is mapped in. This is to avoid
recognition of the pair select command for a
second controller card installed in the same
computer.
The select information is contained in address
line 0, thus (if this controller’s EPROM is
switched into $C800—$CFFF) a write to $C800 will
select Bank 0 (drives 1 and 2). A write to
$C801 will select Bank 1 (drives 3 and 4) a
condition which will be indicated by an LED.
7 . 2 . 8 . D a t a B u f f e r / I n t e r n a l D a t a B u s
The data buffer U13 (8304) is powered-on when-
ever a data transfer to or from the controller
card occurs. The internal data bus connects the
data buffer with the EPROM and the serial to
parallel converter U12 (74LS323). The outputs
P a g e 7 - 1 2