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Quectel Smart Module Series, Hardware Design

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                                                          Smart Module Series 

                                                                                                          SA800U-WF Hardware Design

 

SA800U-WF_Hardware_Design                                                                                                              98 / 106

 

 
 

7.3. Top and Bottom View of the Module 

 

Figure 37: Top View of SA800U-WF Module 

 

 

Figure 38: Bottom View of SA800U-WF Module 

 

 

Images  above  are  for  illustration  purpose  only  and  may  differ  from  the  actual  module.  For  authentic 

appearance and label, please refer to the module received from Quectel. 

NOTE   

Summary of Contents for Smart Module Series

Page 1: ...SA800U WF Hardware Design Smart Module Series Version 1 0 Date 2021 01 13 Status Released www quectel com...

Page 2: ...or notice Disclaimer While Quectel has made efforts to ensure that the functions and features under development are free from errors it is possible that these functions and features could contain erro...

Page 3: ...Quectel Transmitting reproducing disseminating and editing this document as well as using the content without permission are forbidden Offenders will be held liable for payment of damages All rights...

Page 4: ...may cause interference on sensitive medical equipment so please be aware of the restrictions on the use of wireless devices when in hospitals clinics or other healthcare facilities Cellular terminals...

Page 5: ...ware Design SA800U WF_Hardware_Design 4 106 About the Document Revision History Version Date Author Description 2020 07 31 Light WANG Finley ZHANG Creation of the document 1 0 2021 01 13 Light WANG Fi...

Page 6: ...ase Voltage Drop 38 3 4 3 Reference Design for Power Supply 39 3 5 Turn on and off Scenarios 40 3 5 1 Turn on the Module Using PWRKEY 40 3 5 2 Turn on the Module Automatically Using CBL_PWR_N 42 3 5 3...

Page 7: ...nna Connection 86 5 1 Antenna Connectors 86 5 2 Antenna Installation 87 5 2 1 Antenna Requirements 87 5 2 2 Recommended Mating Plug for Antenna Connection 88 6 Reliability Radio and Electrical Charact...

Page 8: ...19 Pin Definition of ADC Interfaces 62 Table 20 Pin Definition of Vibrator Drive Interface 62 Table 21 Pin Definition of LCM Interfaces 63 Table 22 Pin Definition of Touch Panel Interface 67 Table 23...

Page 9: ...Smart Module Series SA800U WF Hardware Design SA800U WF_Hardware_Design 8 106 Table 42 Tray Package 101 Table 43 Related Documents 102 Table 44 Terms and Abbreviations 102...

Page 10: ...Figure 19 PCIe Interfaces Reference Circuit 56 Figure 20 Reference Circuit for SD Card Interface 58 Figure 21 Reference Circuit for Vibrator Connection 63 Figure 22 Reference Circuit Design for LCM0 I...

Page 11: ...le and describes its air interfaces and hardware interfaces This document helps you quickly understand module interface specifications electrical and mechanical details as well as other related inform...

Page 12: ...low power Snapdragon sensor core DSP to support always on use cases Provide multiple audio and video input output interfaces as well as abundant GPIO interfaces The following table shows the supporte...

Page 13: ...4 V Typ 3 8 V WLAN Features 2 4 5 GHz 802 11a b g n ac Support 2 2 MIMO maximally up to 866 Mbps Support AP and STA modes Bluetooth Features BT 2 1 EDR 3 0 4 1 LE 4 2 BLE BT 5 0 LCM Interfaces Suppor...

Page 14: ...omplies with SD 3 0 specifications I2C Interfaces 6 I2C interfaces used for peripherals such as TP camera sensor etc I2S Interfaces 3 I2S interfaces Flashlight Interfaces 3 high current flash LED driv...

Page 15: ...Functional Diagram The following figure shows a block diagram of SA800U WF and illustrates the major functional parts Power management Baseband LPDDR4X UFS flash Peripheral interfaces USB interfaces P...

Page 16: ...A_1V8 SD_LDO21A LVS1A_1V8 LVS2A_1V8 LDO19A_3V0 LDO24A_3V075 LDO14A_1V88 LDO28A_3V0 Audio 38 4M FM ANT RGB RGB WLED Battery Display Bias VDISP XO 38 4M 2 PCIe 2 SDIO RFFE 1 Wi Fi MIMO ANT BT ANT PDET_I...

Page 17: ...orm The following chapters provide the detailed description of interfaces listed below Power supply VRTC interface Charging interface USB interfaces UART interface PCIe interfaces SD card interface GP...

Page 18: ...J2 18 J2 12 J2 16 J2 20 J2 26 J2 22 J2 24 J2 28 J2 34 J2 30 J2 32 J2 36 J2 42 J2 38 J2 40 J2 44 J2 50 J2 46 J2 48 J2 52 J2 58 J2 54 J2 56 J2 60 J2 66 J2 62 J2 64 J2 68 J2 74 J2 70 J2 72 J2 76 J2 82 J2...

Page 19: ...Input DO Digital Output DIO Digital Input Output OD Open Drain PI Power Input PO Power Output Power Supply Pin Name Pin No I O Description DC Characteristics Comment VBAT J1 159 J1 160 J1 161 J1 162 J...

Page 20: ...IOmax 100 mA Power supply for IOVDD or VDD of sensors Add a 1 0 2 2 F bypass capacitor if used If unused keep this pin open LDO12A_1V8 J3 12 PO 1 8 V output Vnom 1 8 V IOmax 300 mA Connect this pin to...

Page 21: ...0 J1 83 J1 89 J1 93 J1 94 J1 97 J1 101 J1 105 J1 113 J1 119 J1 125 J1 131 J1 156 J1 157 J1 158 J2 11 J2 12 J2 17 J2 18 J2 23 J2 24 J2 29 J2 30 J2 35 J2 36 J2 41 J2 42 J2 45 J2 53 J2 98 J2 103 J2 104 J...

Page 22: ...ceive USB1_SS1_RX_P J2 120 AI USB1 3 1 channel 1 super speed receive USB1_SS2_TX_M J2 111 AO USB1 3 1 channel 2 super speed transmit USB1_SS2_TX_P J2 113 AO USB1 3 1 channel 2 super speed transmit USB...

Page 23: ...SB2 3 1 channel 1 super speed receive PCIe Interfaces Pin Name Pin No I O Description DC Characteristics Comment PCIE0_RST_N J1 1 DO PCIe0 reset VOLmax 0 45 V VOHmin 1 35 V PCIE0_WAKE_N J1 3 DI PCIe0...

Page 24: ...cription DC Characteristics Comment SDC4_CLK J1 86 DO SDIO clock VOLmax 0 45 V VOHmin 1 35 V SDIO function is not supported by default Can be multiplexed into GPIOs SDC4_CMD J1 92 DO SDIO command VOLm...

Page 25: ...1 8 2 95 V output power for SD card pull up circuits Vnom 1 8 2 95 V IOmax 50 mA TP Touch Panel Interface Pin Name Pin No I O Description DC Characteristics Comment TP_INT J2 48 DI TP interrupt VILma...

Page 26: ...28 AO LCD0 MIPI clock DSI0_LN0_N J2 38 AO LCD0 MIPI lane 0 data DSI0_LN0_P J2 40 AO LCD0 MIPI lane 0 data DSI0_LN1_N J2 32 AO LCD0 MIPI lane 1 data DSI0_LN1_P J2 34 AO LCD0 MIPI lane 1 data DSI0_LN2_N...

Page 27: ...mera 0 CSI0_LN0_N J1 22 AI MIPI lane 0 data of camera 0 CSI0_LN0_P J1 24 AI MIPI lane 0 data of camera 0 CSI0_LN1_N J1 16 AI MIPI lane 1 data of camera 0 CSI0_LN1_P J1 18 AI MIPI lane 1 data of camera...

Page 28: ..._LN1_N J1 66 AI MIPI lane 1 data of camera 2 CSI2_LN1_P J1 64 AI MIPI lane 1 data of camera 2 CSI2_LN2_N J1 72 AI MIPI lane 2 data of camera 2 CSI2_LN2_P J1 70 AI MIPI lane 2 data of camera 2 CSI2_LN3...

Page 29: ...of camera 2 CAM0_RST J1 100 DO Reset of camera 0 CAM1_RST J1 96 DO Reset of camera 1 CAM2_RST J1 124 DO Reset of camera 2 CAM3_RST J1 126 DO Reset of camera 3 CAM0_PWDN J1 114 DO Power down of camera...

Page 30: ...VILmax 0 63 V VIHmin 1 17 V Pulled up to 1 8 V internally Active low VOL_UP J2 9 DI Volume up If unused keep this pin open VOL_DOWN J2 7 DI Volume down If unused keep this pin open HOME_KEY J2 145 DI...

Page 31: ...ave in SSC_SPI2_MISO J1 147 DI Sensor core SPI2 master in salve out VILmax 0 63 V VIHmin 1 17 V MAG_INT J1 133 DI Magnetic sensor interrupt MAG_DRDY_INT J1 135 DI Magnetic sensor DRDY interrupt GYRO_I...

Page 32: ...47 k resistor BAT_P J2 163 AI Battery voltage detect Must be connected BAT_M J2 165 AI Battery voltage detect CS_P J2 157 AI Current sense CS_M J2 159 AI Current sense BAT_RBIAS J3 11 PO Power supply...

Page 33: ...CODEC_RST J2 90 DO Codec reset VOLmax 0 45 V VOHmin 1 35 V 1 8 V power domain CODEC_INT1 J2 91 DI Codec interrupt 1 VILmax 0 63 V VIHmin 1 17 V CODEC_INT2 J2 93 DI Codec interrupt 2 CODEC_SPI_CS J2 9...

Page 34: ...I2S2_DATA1 J2 61 DIO I2S2 data channel 1 I2S3_WS J2 63 DO I2S3 word select VOLmax 0 45 V VOHmin 1 35 V I2S3_SCK J2 73 DO I2S3 bit clock I2S3_DATA0 J2 69 DIO I2S3 data channel 0 VILmax 0 63 V VIHmin 1...

Page 35: ...SPI2_CLK J2 52 DO SPI2 clock VOLmax 0 45 V VOHmin 1 35 V 1 8 V power domain SPI2_CS J2 54 DO SPI2 chip select SPI2_MOSI J2 58 DO SPI2 master out slave in SPI2_MISO J2 56 DI SPI2 master in salve out VI...

Page 36: ...DO DisplayPort auxiliary channel switch output enable VOLmax 0 45 V VOHmin 1 35 V 1 8 V power domain SBU_SW_SEL J2 3 DO DisplayPort auxiliary channel switch select Vibrator Drive Interface Pin Name P...

Page 37: ...ch modes FLASH_LED2 J4 20 J4 21 AO Flash torch driver output 2 ILED2 1 5 A FLASH_LED3 J4 5 J4 6 AO Flash torch driver output 3 ILED3 0 75 A VRTC Interface Pin Name Pin No I O Description DC Characteri...

Page 38: ...bles CBL_PWR_N J1 134 DI Initiates power on when grounded DBG_TXD J2 137 DO Debug UART transmit VOLmax 0 45 V VOHmin 1 35 V 1 8 V power domain DBG_RXD J2 135 DI Debug UART receive VILmax 0 63 V VIHmin...

Page 39: ...s below 3 1 V the module will be powered off automatically Therefore make sure the input voltage will never drop below 3 1 V 3 1 V Voltage 3 8 V Input current 3 A Figure 3 Voltage Drop Sample To decre...

Page 40: ...is not used it is recommended to use a regulator for the module If the voltage difference between the input and output is not too high it is suggested to use an LDO to supply power for the module If...

Page 41: ...between the output of the inductor L1 and the VBAT pins of the module 3 When the battery voltage is below 3 1 V the system will trigger automatic shutdown so the design of power supply should be cons...

Page 42: ...SD protection A reference circuit is shown in the following figure PWRKEY S1 Close to S1 TVS 1K Figure 7 Turn on the Module Using Keystroke The timing of turning on is illustrated in the following fig...

Page 43: ...PWRKEY Additionally PWRKEY cannot be pulled down all the time 3 5 2 Turn on the Module Automatically Using CBL_PWR_N The module can be turned on automatically by driving the CBL_PWR_N pin to GND throu...

Page 44: ...llustrated in the following figure VBAT PWRKEY Others 8 s Restart Figure 10 Timing of Restarting the Module 3 6 VRTC Interface The RTC Real Time Clock can be powered by an external power source throug...

Page 45: ...should be less than 2 k and it is recommended to use the MS621FE FL11E of SEIKO 3 7 Power Output SA800U WF supports output of regulated voltages for peripheral circuits During application it is recom...

Page 46: ...hen the battery voltage is between the maximum pre charge voltage and 4 35 V 3 0 4 35 V programmable 4 35 V by default the system will switch to CC mode The charging current is programmable from 300 4...

Page 47: ...ust be connected BAT_M J2 165 AI Battery voltage detect CS_P J2 157 AI Current sense CS_M J2 159 AI Current sense BAT_RBIAS J3 11 PO Power supply for NTC pull up circuit If NTC 10 k pull BAT_THERM up...

Page 48: ...you to estimate the battery life based on the battery level to timely save important data before complete power down Mobile devices such as mobile phone and game machine systems are powered by batteri...

Page 49: ...ough USB_SS1 when it is plugged in with the other side up USB_CC2 will detect the external device and the data will be transmitted through USB_SS2 The following table shows the pin definition of USB T...

Page 50: ...F can support E mark cable and active cable Table 8 Pin Definition of VCONN Circuit USB1_SS2_TX_M J2 111 AO USB1 3 1 channel 2 super speed transmit USB1_SS2_TX_P J2 113 AO USB1 3 1 channel 2 super spe...

Page 51: ...rt mode with 4 lanes up to 4K 60 fps over USB Type C The pin definition of USB Type C DisplayPort mode is listed below Table 9 Pin Definition of USB Type C DisplayPort Mode Pin Name USB Type C Mode Di...

Page 52: ..._1V8 0 1 F 0 1 F Module 1 F SBU1 SBU2 2 2K SGM7227YMS10G TR SBU_SW_SEL C3 C4 C5 C6 C1 C2 R1 R1 R3 C3 Figure 15 DisplayPort Reference Design 3 9 2 USB2 Interface USB2 only supports host mode The follow...

Page 53: ...nce Design USB2 for Host Mode 3 9 3 Design Principles Table 11 USB Trace Length Inside the Module USB2_SS_RX_M J2 100 AI USB2 3 1 channel 1 super speed receive USB2_SS_RX_P J2 102 AI USB2 3 1 channel...

Page 54: ...es Do not route USB 3 1 signal lines under RF signal lines Crossing or parallel with RF signal lines is forbidden Isolation between USB 3 1 signals and RF signals should be more than 90 dB Otherwise t...

Page 55: ...D B1 B2 VREG_S4A_1V8 DBG_RXD DBG_TXD RXD _3 3V TXD _3 3V VDD _3 3V TXS0102DCUR C1 100 pF C2 U1 100 pF Figure 17 Reference Circuit with Level Translator Chip The following figure is an example of conne...

Page 56: ...PCIE0_REFCLK_P J1 15 AO PCIe0 reference clock Control the characteristic impedance as 85 PCIE0_REFCLK_M J1 17 AO PCIe0 reference clock PCIE0_TX_P J1 11 AO PCIe0 transmit PCIE0_TX_M J1 9 AO PCIe0 trans...

Page 57: ...Circuit To enhance the reliability and availability in applications follow the criteria below in the circuit design of PCIe interfaces Keep the PCIe signals away from noisy signals such as clock signa...

Page 58: ...SD_LDO13A J4 11 PO 1 8 2 95 V output power for SD card pull up circuits Vnom 1 8 2 95 V IOmax 50 mA SD_CLK J1 45 DO SD card clock Control characteristic impedance as 45 SD_CMD J1 47 DO SD card comman...

Page 59: ...rive power a 4 7 F and a 33 pF capacitor should be added in parallel near the SD card connector SD_CMD SD_CLK SD_DATA0 SD_DATA1 SD_DATA2 and SD_DATA3 are all high speed signal lines In PCB design cont...

Page 60: ..._DATA3 14 10 Pin Name Pin No I O Description Comment GPIO_25 J2 2 DIO General purpose input output GPIO_42 J2 64 DIO General purpose input output GPIO_44 J2 66 DIO General purpose input output Wakeup...

Page 61: ...dedicated to support low power and always on use cases Table 17 Pin Definition of I2C Interfaces GPIO_135 J2 134 DIO General purpose input output Pin Name Pin No I O Description Comment TP_I2C_SCL J2...

Page 62: ...DO SPI2 clock 1 8 V power domain SPI2_CS J2 54 DO SPI2 chip select SPI2_MISO J2 56 DI SPI2 master in salve out SPI2_MOSI J2 58 DO SPI2 master out slave in SPI0_CLK J2 86 DO SPI0 clock SPI0_CS J2 80 D...

Page 63: ...ve Interface SA800U WF supports eccentric rotating mass ERM motor and linear resonant actuator LRA The pin definition of vibrator drive interface is listed below Table 20 Pin Definition of Vibrator Dr...

Page 64: ...s 8 lanes can support QUXGA display resolution 3840 2160 The module supports dual LCD independent display default DSI DP over USB Type C optional DSI0 DSI1 Please note that DSI1 does not support scree...

Page 65: ...2 37 AO LCD1 MIPI lane 1 data DSI1_LN1_P J2 39 AO LCD10 MIPI lane 1 data DSI1_LN2_N J2 27 AO LCD1 MIPI lane 2 data DSI1_LN2_P J2 25 AO LCD1 MIPI lane 2 data DSI1_LN3_N J2 31 AO LCD1 MIPI lane 3 data D...

Page 66: ..._TDN3 GND MIPI_TDP2 MIPI_TDN2 GND MIPI_TDP1 MIPI_TDN1 GND LCD_BL_A LCD_BL_K1 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 MIPI_TDP0 MIPI_TDN0 GND MIPI_TCP MIPI_TCN 29 28 30 3 4...

Page 67: ...2 F R1 Figure 23 Reference Circuit Design for LCM1 Interface MIPI are high speed signals It is recommended that common mode filters should be added in series near the LCM connector so as to improve pr...

Page 68: ...M_PMI_GPIO5 Module 2 2 F Backlight Driver LCM1_LED VBAT C1 R1 10K Figure 24 Reference Design of LCM1 External Backlight Driving Circuit 3 19 Touch Panel Interface SA800U WF provides one I2C interface...

Page 69: ...P The 2 lane MIPI CSI can only receive data of RAW format It can be used for ToF 3D camera modules and cannot be used for display The video and photo quality are determined by various factors such as...

Page 70: ...f camera 1 CSI1_LN2_N J1 42 AI MIPI lane 2 data of camera 1 CSI1_LN2_P J1 40 AI MIPI lane 2 data of camera 1 CSI1_LN3_N J1 34 AI MIPI lane 3 data of camera 1 CSI1_LN3_P J1 36 AI MIPI lane 3 data of ca...

Page 71: ...118 DO Strobe of camera 2 CAM0_MCLK J1 91 DO Master clock of camera 0 CAM1_MCLK J1 95 DO Master clock of camera 1 CAM2_MCLK J1 99 DO Master clock of camera 2 CAM3_MCLK J1 103 DO Master clock of camer...

Page 72: ...I0_ LN0_N CSI0_ LN1_P CSI0_ LN1_N CSI0_ LN2_P CSI0_ LN2_N CSI0_ LN3_P CSI0_ LN3_N CAM0_AVDD CAM0_AF_VDD CAM0_DVDD LVS1A_1V8 AFVDD MODULE CAM0_STROBE 1 F 4 7 F 4 7 F R1 R2 C1 C2 C3 C4 Figure 26 Referen...

Page 73: ...EN R1 100K C2 CAM0_DVDD Module 2 2 F DCDC_IC VBAT C5 CAM0_DVDD_EN R3 100K C6 CAM0_AVDD Module 2 2 F LDO_IC VBAT C3 R2 100K C4 CAM0_AVDD_EN L1 2 2 F 2 2 F 2 2 F Figure 27 Reference Circuit Design for P...

Page 74: ...s keep all the MIPI traces of the same length Route the CAM_MCLK signals in the inner layer of the PCB and surround them with ground Spacing for the lanes should comply with the following rules a Intr...

Page 75: ...is listed above 3 The maximum PCB trace length listed above includes the length routed inside the module Table 26 MIPI Trace Length Inside the Module Data Rate Flex Cable Length inch Cable Insertion...

Page 76: ...9 J2 15 DSI1_LN0_P 22 71 J2 37 DSI1_LN1_N 23 35 0 67 J2 39 DSI1_LN1_P 24 02 J2 27 DSI1_LN2_N 22 45 0 54 J2 25 DSI1_LN2_P 22 99 J2 31 DSI1_LN3_N 23 73 0 46 J2 33 DSI1_LN3_P 23 27 J1 30 CSI0_CLK_N 23 90...

Page 77: ...1 34 CSI1_LN3_N 15 61 0 30 J1 36 CSI1_LN3_P 15 31 J1 63 CSI2_CLK_N 16 36 0 36 J1 61 CSI2_CLK_P 16 72 J1 67 CSI2_LN0_N 15 84 0 25 J1 69 CSI2_LN0_P 16 09 J1 66 CSI2_LN1_N 15 71 0 40 J1 64 CSI2_LN1_P 16...

Page 78: ...0 mA for each whether the two LEDs work together or separately As for FLASH_LED3 in flash mode the maximum output current is 0 75 A and in torch mode the maximum output current is 500 mA Table 27 Pin...

Page 79: ...n Comment SSC_SPI1_CS0 J1 136 DO Sensor core SPI1 chip select 0 1 8 V power domain SSC_SPI1_CS1 J1 138 DO Sensor core SPI1 chip select 1 SSC_SPI1_CS2 J1 140 DO Sensor core SPI1 chip select 2 SSC_SPI1_...

Page 80: ...EC_SPI_CLK J2 92 DO SPI clock for codec CODEC_SPI_MOSI J2 94 DO SPI master out slave in for codec CODEC_SPI_CS J2 96 DO SPI chip select for codec CODEC_SPI_MISO J2 89 DI SPI master in salve out for co...

Page 81: ...l startup or operation For convenient firmware upgrade and debugging in the future please reserve the reference circuit design shown as below VREG_S4A_1V8 S1 Module USB_BOOT R1 10K Figure 29 Reference...

Page 82: ...mic antenna can be connected to the module via these connectors so as to achieve Wi Fi and BT functions means under development 4 1 Wi Fi Overview SA800U WF supports 2 4 GHz and 5 GHz dual band WLAN w...

Page 83: ...B 802 11g 54 Mbps 14 dBm 2 5 dB 802 11n HT20 MCS0 16 dBm 2 5 dB 802 11n HT20 MCS7 13 dBm 2 5 dB 802 11n HT40 MCS0 16 dBm 2 5 dB 802 11n HT40 MCS7 13 dBm 2 5 dB 5 GHz 802 11a 6 Mbps 17 dBm 2 5 dB 802 1...

Page 84: ...ps 96 dBm 802 11b 11 Mbps 87 dBm 802 11g 6 Mbps 90 dBm 802 11g 54 Mbps 74 dBm 802 11n HT20 MCS0 90 dBm 802 11n HT20 MCS7 72 dBm 802 11n HT40 MCS0 87 dBm 802 11n HT40 MCS7 70 dBm 5 GHz 802 11a 6 Mbps 9...

Page 85: ...ommodate 79 channels The BLE channel bandwidth is 2 MHz and can accommodate 40 channels Table 32 BT Data Rate and Versions Reference specifications are listed below Bluetooth Radio Frequency TSS and T...

Page 86: ...the BT transmitting and receiving performance of SA800U WF module Table 33 BT Transmitting and Receiving Performance Transmitter Performance Packet Types DH5 2 DH5 3 DH5 Transmitting Power 7 5 dBm 2...

Page 87: ...nector ANT CH1 Wi Fi MIMO antenna connector BT BT antenna connector and FM FM antenna connector respectively The impedance of the antenna connectors is 50 Figure 30 Antenna Connectors Table 34 Definit...

Page 88: ...ows the requirements for Wi Fi BT FM antennas Table 36 Antenna Requirements BT AIO BT antenna connector 50 impedance FM AI FM antenna connector 50 impedance Type Frequency Unit 802 11a b g n ac 2402 2...

Page 89: ...2 2 Recommended Mating Plug for Antenna Connection SA800U WF is mounted with RF connectors receptacles for convenient antenna connection The connector being used is 818000500 from ECT and its dimensio...

Page 90: ...Module Series SA800U WF Hardware Design SA800U WF_Hardware_Design 89 106 The mating plug listed in the following figure can be used to match the receptacles Figure 32 Mechanicals of the Mating Plug Un...

Page 91: ...olute Maximum Ratings 6 2 Power Supply Ratings Table 38 SA800U WF Power Supply Ratings Parameter Min Max Unit VBAT 0 3 6 V USB_VBUS 0 3 28 V Voltage on Digital Pins 0 5 2 3 V Parameter Description Con...

Page 92: ...nsumption The current consumption of different conditions is listed in the following table Table 40 SA800U WF Current Consumption 2 2 MIMO USB_VBUS Charging power input Power output for OTG device USB...

Page 93: ...z 770 mA 300 Mbps 40 MHz 615 mA Wi Fi 802 11ac Tx 14 4 Mbps 20 MHz 760 mA 173 2 Mbps 20 MHz 655 mA 30 Mbps 40 MHz 740 mA 400 Mbps 40 MHz 610 mA 65 Mbps 80 MHz 685 mA 866 6 Mbps 80 MHz 565 mA Wi Fi 802...

Page 94: ...itions such as with maximum power for a long time it is strongly recommended to apply thermal conductive gap fillers to the gaps between the shielding cover and heat generating components in the modul...

Page 95: ...lowing figure shows the thermal dissipation area Figure 33 Thermal Dissipation If a conformal coating is necessary for the module do NOT use any coating material that may chemically react with the PCB...

Page 96: ...Mechanical Dimensions This chapter describes the mechanical dimensions of the module All dimensions are measured in millimeter mm and the dimension tolerances are 0 05 mm unless otherwise specified 7...

Page 97: ...Smart Module Series SA800U WF Hardware Design SA800U WF_Hardware_Design 96 106 Figure 35 Module Bottom Dimensions Bottom View...

Page 98: ...commended Footprint Top View 1 For easy maintenance of the module keep about 5 mm between the module and other components on the host PCB 2 All RESERVED pins should be kept open and MUST NOT be connec...

Page 99: ...and Bottom View of the Module Figure 37 Top View of SA800U WF Module Figure 38 Bottom View of SA800U WF Module Images above are for illustration purpose only and may differ from the actual module For...

Page 100: ...uld be 35 60 2 The storage life in vacuum sealed packaging is 12 months in Recommended Storage Condition 3 The floor life of the module is 168 hours 1 in a plant where the temperature is 23 5 C and re...

Page 101: ...esign SA800U WF_Hardware_Design 100 106 8 2 Packaging SA800U WF is packaged in tray carriers Each tray is 350 mm 245 mm 15 8 mm and contains 18 modules The following figures show the package details m...

Page 102: ...U WF_Hardware_Design 101 106 10 trays are overlaid in one vacuum sealed package The package details are shown below Figure 40 Package Details Table 42 Tray Package Model Name MOQ for MP Minimum Packag...

Page 103: ...SA800U WF 2 Quectel_SA800U WF_Pin_Description_and_GPIO_ Configuration Pin Description and GPIO Configuration of SA800U WF 3 Quectel_SA800U WF_Reference_Design Reference Design for SA800U WF Abbreviat...

Page 104: ...rostatic Discharge ESR Equivalent Series Resistance EVRC Enhanced Variable Rate Codec EVS Enhanced Voice Services FM Frequency Modulation GPIO General Purpose Input Output GPU Graphics Processing Unit...

Page 105: ...r Ceramic Capacitor NTC Negative Temperature Coefficient OTG On The Go OVP Over Voltage Protection PCB Printed Circuit Board PCIe Peripheral Component Interconnect Express PHY Physical Layer PMU Power...

Page 106: ...iversal Asynchronous Receiver Transmitter UFS Universal Flash Storage USB Universal Serial Bus VESA Video Electronics Standards Association VHT Very High Throughput Vmax Maximum Voltage Value Vnom Nom...

Page 107: ...Output High Level Voltage Value VOHmin Minimum Output High Level Voltage Value VOLmax Maximum Output Low Level Voltage Value VOLmin Minimum Output Low Level Voltage Value WAPI WLAN Authentication and...

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