Smart Module Series
SA800U-WF Hardware Design
SA800U-WF_Hardware_Design 71 / 106
The following is a reference circuit design for camera applications.
R
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c
a
m
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c
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CAM0_PWDN
CAM0_MCLK
CCI0 _I2C_SDA
CCI0 _ I2C_ SCL
CSI0_ CLK_P
CSI0_ CLK_N
2.2K
2.2K
CAM0_RST
EMI
EMI
EMI
EMI
EMI
AVDD
DVDD
DOVDD
1
μ
F
CSI0_ LN0_P
CSI0_ LN0_N
CSI0_ LN1_P
CSI0_ LN1_N
CSI0_ LN2_
P
CSI0_ LN2_
N
CSI0_ LN3_P
CSI0_ LN3_N
CAM0_AVDD
CAM0_AF_VDD
CAM0_DVDD
LVS1A_1V8
AFVDD
MODULE
CAM0_STROBE
1
μ
F
4
.7
μ
F
4
.7
μ
F
R1
R2
C1
C2
C3
C4
Figure 26: Reference Circuit Design for CSI0
CAM1_DVDD_EN
J1-130
DO
DVDD enable of camera 1
CAM2_DVDD_EN
J1-110
DO
DVDD enable of camera 2
CAM3_DVDD_EN
J1-128
DO
DVDD enable of camera 3
CCI0_I2C_SCL
J1-142
OD
CCI0 I2C clock
CCI0_I2C_SDA
J1-144
OD
CCI0 I2C data
CCI1_I2C_SDA
J1-146
OD
CCI1 I2C data
CCI1_I2C_SCL
J1-148
OD
CC1 I2C clock
