Smart Module Series
SA800U-WF Hardware Design
SA800U-WF_Hardware_Design 22 / 106
USB2_DM
J2-107
AIO
USB2 2.0
differential data
(-)
compliant.
Only support host
mode.
USB2_SS_TX_M
J2-108
AO
USB2 3.1
channel 1
super-speed
transmit (-)
90
Ω differential
impedance.
USB 3.1 standard
compliant.
Only support host
mode.
USB2_SS_TX_P
J2-106
AO
USB2 3.1
channel 1
super-speed
transmit (+)
USB2_SS_RX_M
J2-100
AI
USB2 3.1
channel 1
super-speed
receive (-)
USB2_SS_RX_P
J2-102
AI
USB2 3.1
channel 1
super-speed
receive (+)
PCIe Interfaces
Pin Name
Pin No.
I/O
Description
DC Characteristics Comment
PCIE0_RST_N
J1-1
DO
PCIe0 reset
V
OL
max = 0.45 V
V
OH
min = 1.35 V
PCIE0_WAKE_N
J1-3
DI
PCIe0 wake up
host
V
IL
max = 0.63 V
V
IH
min = 1.17 V
PCIE0_CLKREQ_N
J1-5
DI
PCIe0 clock
request
V
IL
max = 0.63 V
V
IH
min = 1.17 V
PCIE0_REFCLK_P
J1-15
AO
PCIe0 reference
clock (+)
Control the
characteristic
impedance as
85
Ω.
PCIE0_REFCLK_M
J1-17
AO
PCIe0 reference
clock (-)
PCIE0_TX_P
J1-11
AO
PCIe0 transmit
(+)
PCIE0_TX_M
J1-9
AO
PCIe0 transmit
(-)
PCIE0_RX_P
J1-21
AI
PCIe0 receive
(+)
PCIE0_RX_M
J1-23
AI
PCIe0 receive (-)
PCIE1_RST_N
J1-107
DO
PCIe1 reset
V
OL
max = 0.45 V
V
OH
min = 1.35 V
