Smart Module Series
SA800U-WF Hardware Design
SA800U-WF_Hardware_Design 56 / 106
PCIE_REFCLK_P
PCIE_REFCLK_M
PCIE_RX_P
PCIE_RX_M
PCIE_TX_P
PCIE_TX_M
PCIE0_REFCLK_P
PCIE0_REFCLK_M
PCIE0_RX_P
PCIE0_RX_M
PCIE0_TX_P
PCIE0_TX_M
PCIE0_CLKREQ_N
PCIE0_RST_N
PCIE0_WAKE_N
PCIE_CLKREQ_N
PCIE_RST_N
PCIE_WAKE_N
C1
C2
PCIE_REFCLK_P
PCIE_REFCLK_M
PCIE_RX_P
PCIE_RX_M
PCIE_TX_P
PCIE_TX_M
PCIE1_REFCLK_P
PCIE1_REFCLK_M
PCIE1_RX_P
PCIE1_RX_M
PCIE1_TX_P
PCIE1_TX_M
PCIE1_CLKREQ_N
PCIE1_RST_N
PCIE1_WAKE_N
PCIE_CLKREQ_N
PCIE_RST_N
PCIE_WAKE_N
VREG_S4A_1V8
R1
1K
R2
10K
R3
10K
C3
C4
optional
RTL8111H
Module
Figure 19: PCIe Interfaces Reference Circuit
To enhance the reliability and availability in applications, follow the criteria below in the circuit design of
PCIe interfaces:
Keep the PCIe signals away from noisy signals, such as clock signals, SMPS, and so forth.
It is recommended to place the AC coupling capacitors (C1/C2/C3/C4) close to the TX side to ensure
signal integrity of trace routing on PCB.
Keep the intra-pair length difference within each differential data pair less than 0.7 mm during PCIe
trace routing.
Trace length matching between the reference clock, TX, and RX pairs is not required.
Keep the impedance of PCIe differential traces
as 85 Ω ±10 %.
You must not route PCIe data traces under components or cross them with other traces.
The spacing between PCIe signals and all other signals and that between RX and TX should be at
least 4 times the trace width.
