Smart Module Series
SA800U-WF Hardware Design
SA800U-WF_Hardware_Design 58 / 106
A reference circuit for SD card interface is shown as below.
SD_CMD
120K
NM_51K
SD_DATA3
SD_DATA2
VREG_S4A_1V8
SD_CLK
SD_DATA0
SD_DET
SD_DATA1
P1-DAT2
P2-CD/DAT3
P3-CMD
P4-VDD
P5-CLK
P8-DAT1
GND
P6-VSS
P7-DAT0
DETECTIVE
GND
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
SD_LDO21A
33R
33R
33R
33R
33R
33R
1K
33 pF
4.7
μ
F
SD_LDO13A
Module
R1
R2
R3
R4
R5
R6
NM_51K NM_10K NM_51K NM_51K
R7
R8
R9
R10
R11
R12
R13
D1
D2
D3
D4
D5
D6
D7
D8
C1
C2
SD Card Connector
Figure 20: Reference Circuit for SD Card Interface
SD_LDO21A is a peripheral power supply driver for SD card. The maximum drive current is about 800 mA.
Because of the high drive current, it is recommended that the trace width should be 0.8 mm or above. To
ensure the stability of drive power, a 4.7
μF and a 33 pF capacitor should be added in parallel near the SD
card connector.
SD_CMD, SD_CLK, SD_DATA0, SD_DATA1, SD_DATA2 and SD_DATA3 are all high speed signal lines.
In PCB design, control the characteristic impedance of them to 45
Ω, and do not cross them with other
traces. It is recommended to route these traces on the inner layer of PCB, and keep them of the same
trace length. Additionally, SD_CLK needs separate ground shielding.
Layout guidelines:
Control characteristic impedance to 45
Ω ±10 %, and add ground shielding.
The length difference between SD_CLK and SD_DATA should be less than 2 mm.
The spacing between SDIO signals and all other signals and that between different SDIO signals
should be at least 1.5 times the trace width.
For SDR104 mode, the total routing length recommended is less than 50 mm, and the total
capacitance should be less than 5 pF
For SDR50 and DDR50 modes, the total routing length recommended is less than 150 mm, and the
total capacitance should be less than 10 pF
