Smart Module Series
SA800U-WF Hardware Design
SA800U-WF_Hardware_Design 73 / 106
3.20.1. Design Considerations
Special attention should be paid to the pin definition of LCM/camera connectors. Ensure the
SA800U-WF module and the connectors are correctly connected.
MIPI are high-speed signals, supporting maximum data rate of up to 2.5 Gbps. The differential
impedance should be controlled as 100
Ω. Additionally, it is recommended to route the trace on the
inner layer of PCB, and do not cross it with other traces. Any cut or hole on GND reference plane
under MIPI signals should be avoided. For the same group of DSI or CSI signals, keep all the MIPI
traces of the same length.
Route the CAM_MCLK signals in the inner layer of the PCB and surround them with ground.
Spacing for the lanes should comply with the following rules:
a) Intra-lane P to N: 1 × trace width
b) Lane to lane: 1.5 × trace width
c) Lanes to all other signals: 2.5 × trace width
Route MIPI traces according to the following rules:
a) Control the differential impedance to 100
Ω ±10 %;
b) Control intra-lane length difference within 0.7 mm;
c) Control inter-lane length difference within 1.4 mm.
Table 24: CSI Data Rate and PCB Maximum Trace Length (D-PHY)
Data Rate
Flex Cable Length
(inch)
Cable Insertion Loss
(dB)
Maximum PCB Trace
Length (mm)
500 Mbps/lane
3
-0.5
< 260
6
-1
< 190
750 Mbps/lane
3
-0.7
< 210
6
-1.15
< 155
1.0 Gbps/lane
3
-0.75
< 200
6
-1.4
< 125
1.5 Gbps/lane
3
-0.9
< 145
6
-1.8
< 60
2.1 Gbps/lane
3
-1.3
< 170
6
-2.3
< 90
