Smart Module Series
SA800U-WF Hardware Design
SA800U-WF_Hardware_Design 26 / 106
DSI1_LN2_N
J2-27
AO
LCD1 MIPI lane
2 data (-)
DSI1_LN2_P
J2-25
AO
LCD1 MIPI lane
2 data (+)
DSI1_LN3_N
J2-31
AO
LCD1 MIPI lane
3 data (-)
DSI1_LN3_P
J2-33
AO
LCD1 MIPI lane
3 data (+)
Camera Interfaces
Pin Name
Pin No.
I/O
Description
DC Characteristics Comment
CSI0_CLK_N
J1-30
AI
MIPI clock of
camera 0 (-)
100
Ω differential
impedance.
CSI0_CLK_P
J1-28
AI
MIPI clock of
camera 0 (+)
CSI0_LN0_N
J1-22
AI
MIPI lane 0 data
of camera 0 (-)
CSI0_LN0_P
J1-24
AI
MIPI lane 0 data
of camera 0 (+)
CSI0_LN1_N
J1-16
AI
MIPI lane 1 data
of camera 0 (-)
CSI0_LN1_P
J1-18
AI
MIPI lane 1 data
of camera 0 (+)
CSI0_LN2_N
J1-10
AI
MIPI lane 2 data
of camera 0 (-)
CSI0_LN2_P
J1-12
AI
MIPI lane 2 data
of camera 0 (+)
CSI0_LN3_N
J1-6
AI
MIPI lane 3 data
of camera 0 (-)
CSI0_LN3_P
J1-4
AI
MIPI lane 3 data
of camera 0 (+)
CSI1_CLK_N
J1-58
AI
MIPI clock of
camera 1 (-)
CSI1_CLK_P
J1-60
AI
MIPI clock of
camera 1 (+)
CSI1_LN0_N
J1-52
AI
MIPI lane 0 data
of camera 1 (-)
CSI1_LN0_P
J1-54
AI
MIPI lane 0 data
of camera 1 (+)
CSI1_LN1_N
J1-46
AI
MIPI lane 1 data
of camera 1 (-)
