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RMX-1000
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5. DIAGNOSIS
5.1 POWER ON SEQUENCE
Rough
elapsed time
0
500 ms
Initialization of DSP
650 ms
SH UCOM
DSP
ADC
CDC
DAC
K0R UCOM
POWER ON
Canceling of SH reset
Start up
Start up
Start of K0R communication (primary)
Start of SH communication
Startup mode determined
CPU_MUTE ON
External
factor
State
Action
Switching of K0R communication (for real production)
(Continuation of SH communication)
Initialization according to the determined Startup mod
Canceling of CDC reset
Start up
Start of CDC communication
Start of SH communication
Initialization of CDC
Initialization
From here on, each time
a conversion is finished,
the port for notifying of
conversion completion to
SH is activated.
Canceling of DSP reset
Reset cancel state and standby
Downloading
DSPP&DSPD via HPI
(Standby)
DSP kick-start
Startup begins.
Canceling of ADC reset
Canceling of DAC reset
Start up
Start up
Start up DSP period processing
Canceling of ADC reset (2nd time)
Canceling of DAC reset (2nd time)
Startup (2nd time)
Startup (2nd time)
200 msec wait
5+
α
usec required for
the signal to become
low from high
5+
α
usec required for
the signal to become
high from low
Waiting for completion of DSP
reset cancel
Notifying of reset
cancel by HPIC
Reset state
Reset state
Reset state
Reset state
Reset state
ADC reset
DAC reset
Reset
Reset
FET SW control (for supplying power to
parts other than K0R) is enabled.
DSP outputs a 24-MHz
signal to DAC/ADC.
CLK first, then RST cancel
FET SW set to ON
100 msec wait
100 msec wait
Waits until DSP finishes HPI
communication setting.
Initialization of the peripheral
devices (HPI, etc.)
Initialization of the Cente file system
Initialization of the Cente SD module
ISR registration
CMT interrupt startup
A
Intercommunication