Philips DVDR1000/001, Service Manual

Page: 299 / 317

Circuit-, IC Descriptions and List of Abbreviations
GB 299 DVDR1000 /0x1 /691 9.
Pin # Name Description
SDRAM Interface Signals
125-131 ADDR
10-0
SDRAM Address bus. This signal bus is used to address the external SDRAM(s) used for
133-136 field memories. It should be connected to the A
10-0
bus of the memory chip(s). Please refer
to the Applications section of this data sheet for further details.
176-169 DATA
29-0
SDRAM Data bus. This signal bus is used to transfer the data to and from the external
166-160 SDRAM(s) used for field memories. It should be connected to the DQ
29-0
bus of the memory
157-153 chip when using a 64 Mbit SDRAM. When using two 16 Mbit SDRAMs this 30-bit bus may
150-146 be connected to the two 16-bit data busses of the memories in two ways: either connect 16
143-139 lines to one chip and 14 to the other, or connect 15 to both. In all cases the two unused data
lines on the memory chip(s) should be connected to ground via 22 k resistors. Please refer
to the Applications section of this data sheet for further details.
118 MEMCLKO SDRAM clock and 2x output sampling clock. This clock is derived from PIXCLK and will be at
double the frequency of YCLKO. This active signal should be connected to the CLK pin(s) on
the SDRAM(s). When the 10-bit output mode selected the output signals will also change at
this clock rate and this should then be used as the output clock..
119 WEN SDRAM Write Enable. This active low signal should be connected to the WE pin(s) on the
SDRAM(s).
120 RASN SDRAM Row Address Select. This active low signal should be connected to the RAS pin(s)
on the SDRAM(s).
121 CASN SDRAM Column Address Select. This active low signal should be connected to the CAS
pin(s) on the SDRAM(s).
122 BSEL SDRAM Bank Select. When using two 16 Mbit SDRAMs this signal should be connected to
the BA (also called BS or A
11
) pin on both SDRAMs. When using a 64 Mbit SDRAM this
signal should be connected to the BA0 (also called BS0 or A
11
) pin on the SDRAM and BA1/
BS1 (also called BA when BA0 is referred to as A
11
) should be tied low.
Test Inputs
41, 50, TEST
4-0
These pins are used for test purposes only and should always be tied low for normal operation.
51, 109,
111
Test Outputs
112, 113 TESTO
1-0
These pins are test outputs and should be left unconnected in normal operation.