Philips DVDR1000/001, Service Manual

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Circuit-, IC Descriptions and List of Abbreviations
GB 254 DVDR1000 /0x1 /691 9.
PAL/NTSC/SECAM Video Decoder with Adaptive Comb Filter,
Component Video Input, VBI-Data Slicer and High Performance Scaler
SAA7118
Generation of an audio serial and left/right (channel)
clock signal
Digital I/O Interfaces
Real Time signal port (R - port), incl. continuous line
locked reference clock and real time status information
supporting RTC level 3.1 (refer to external document
“RTC Functional Specification” for details)
Bidirectional Expansion Port (X - port) with half duplex
functionality (D1), 8-bit YCbCr
– output from Decoder part, real time and unscaled, or
– input to Scaler part, e.g. video from MPEG-decoder
(extension to 16 bit possible)
Video Image port (I - port) configurable for 8 - bit data
(extension to 16 bit possible) in Master Mode (own
clock), or Slave Mode (external clock), with auxiliary
timing and hand shake signals
Discontinuous data streams supported
32-word * 4 Byte FIFO register for video output data
28-word * 4 Byte FIFO register for decoded VBI output
data
Scaled 4:2:2, 4:1:1, 4:2:0, 4:1:0 YCbCr output
Scaled 8-bit luminance only and raw CVBS data output
sliced, decoded VBI data output
Miscellaneous
Power On Control
5 V tolerant digital inputs and I/O ports
Software controlled power saving stand-by modes
supported
Programming via serial I
2
C-bus, full read-back ability by
an external controller, bit rate up to 400 kbit/s
Boundary Scan Test circuit complies to the IEEE Std.
1149.b1 -1994
BGA156 package
2 APPLICATIONS
Multimedia
Digital Television
Image Processing
Video Phone
PC- Editing cards
PC- Tuner cards
3 GENERAL DESCRIPTION
Philips X-VIP is a new Multistandard Comb Filter Video
Decoder chip with additional component processing,
providing high quality, optionally scaled, video.
The SAA7118 is a combination of a four channel analog
preprocessing circuit including source selection,
anti-aliasing filter and A/D-converter, an automatic clamp
and gain control, a Clock Generation Circuit (CGC), a
Digital Multi Standard Decoder containing
two-dimensional chrominance/luminance separation by an
adaptive comb filter and a high performance scaler,
including variable horizontal and vertical up and down
scaling and a Brightness- Contrast- Saturation- Control
circuit.
It is a highly integrated circuit for Desktop Video and
similar applications. The decoder is based on the principle
of line-locked clock decoding and is able to decode the
colour of PAL, SECAM and NTSC signals into ITU-601
compatible colour component values. The SAA7118
accepts as analog inputs CVBS or S-Video (Y+C) from TV
or VCR sources, including weak and distorted signals, as
well as baseband component signals YCbCr or RGB. An
expansion port (X-port) for digital video (bi-directional half
duplex, D1 compatible) is also supported to connect to
MPEG or video phone codec. At the so called image port
(I-port) the 7118 supports 8 (16) bit wide output data with
auxiliary reference data for interfacing to VGA controllers.
The target application for SAA7118 is to capture and
optionally scale video images, to be provided as digital
video stream through the image port of a VGA controller,
for capture to system memory, or just to provide digital
baseband video to any picture improvement processing.
SAA7118 also provides means for capturing the serially
coded data in the vertical blanking interval (VBI-data). Two
principal functions are available:
- to capture raw video samples, after interpolation to the
required output data rate, via the scaler and
- a versatile data slicer (data recovery) unit.
SAA7118 incorporates also a field locked audio clock
generation. This function ensures that there is always the
same number of audio samples associated with a field, or
a set of fields. This prevents the loss of sychronization
between video and audio, during capture or playback.
All of the A/D- converters may be used to digitize a VSB
signal for further for further decoding; a dedicated output
port and a selectable VSB clock input is provided.
The circuit is controlled via I
2
C-bus (full write / read
capability for all programming registers, bit rate up to 400
kbits/s)