Philips DVDR1000/001, Service Manual

Page: 261 / 317

Circuit-, IC Descriptions and List of Abbreviations
GB 261 DVDR1000 /0x1 /691 9.
PAL/NTSC/SECAM Video Decoder with Adaptive Comb Filter,
Component Video Input, VBI-Data Slicer and High Performance Scaler
SAA7118
Notes
1. This pin provides easy initialization of BST circuitry. TRSTN can be used to force the TAP (Test Access Port)
controller to the Test-Logic-Reset state (normal operation) at once
2. According to the IEEE1149.b1-1994 standard the pads TDI and TMS are input pads with a internal pull-up transistor
and TDO a tri-state output pad. TCK, TRSTN are also built with internal pile-up
3. Strapping remark: If the strapping pin is unused, the internal pull-down resistor is sufficient for strap function.
If pin is used in an application, an external strapping resistor (4,7k) is necessary to get a certain strap function.
M13 FSW I/pd
Fast Switch (Blanking), with internal pull-down,
inserts component inputs into CVBS signal
M14 ICLK I/O
Clock output signal for image-port, LCLK of LPB image port mode, or optional
asynchronous backend clock input
N01 RES8 NC Reserved pin for future extensions or testing, do not connect
N02 RES9 I/pu Reserved pin for future extensions or testing, do not connect
N03 RES10 I/pd Reserved pin for future extensions or testing, do not connect
N04 CE I/pu Chip Enable or Reset with internal pull-up
N05 LLC2 O Line-locked clock at half frequency (13.5 MHz nominal)
N06 CLKEXT I External clock input intended for A/D-conversion of VSB signals (36 MHz)
N07 ADP5 O MSB-3 of Direct A/D-converted output bus (VSB)
N08 ADP0 O LSB of Direct A/D-converted output bus (VSB)
N09 SCL I I
2
C Serial Clock
N10 RTS1 O Real time status or sync information
N11 ASCLK O Audio serial clock
N12 ITRDY I Target Ready for image port bus
N13 RES11 NC Reserved pin for future extensions or testing, do not connect
N14 RES12 NC Reserved pin for future extensions or testing, do not connect
P02 RES13 I/O Reserved pin for future extensions or testing, do not connect
P03 EXMCLR I/pd External Mode Clear, with internal pull-down
P04 LLC O Line-locked clock (27 MHz nominal)
P05 RESON O Reset Output Not signal
P06 ADP8 O MSB of Direct A/D-converted output bus (VSB)
P07 ADP4 O MSB-4 of Direct A/D-converted output bus (VSB)
P08 ADP1 O MSB-7 of Direct A/D-converted output bus (VSB)
P09 INT_A O/od I
2
C interrupt flag (Low if any enabled status bit has changed)
P10 SDA I/O/od I
2
C Serial Data
P11 AMCLK O Audio Master clock, must be less than half the crystal clock frequency
P12
ALRCLK
O/st/pd Audio left/right clock,
strap to LOW (4k7) for 24.576 MHz crystal
strap to HIGH (4k7) for 32.11 MHz crystal (3)
P13 TEST0 I/pu Scan test input; do not connect
TYPE description:
I=input, O=output, P=power, NC=not connected, st=strapping, pu=pull-up, pd=pull-down, od=open drain
PIN NAME TYPE DESCRIPTION