CP302
Functional Description and Configuration
ID 21112, Rev. 05
Page 2 - 36
®
PEP Modular Computers GmbH
2.9.1.2 Watchdog Timer
The CP302 has one watchdog timer with a programmable timeout ranging from 125
msec. to 256 sec.
The I/O location for the watchdog configuration is 0x282.
2.9.2
Reset Control Register
This register controls the reset signal for the Ethernet controller and the VGA-AGP
interface. A low signal keeps the chips in the reset mode. The default configuration is
high.
The I/O location for the reset control register is 0x281.
Table 2-24: Watchdog Configuration
Bits
Type
Default
Function
7-5
R
0
Reserved
4
RW
0
1 = enable watchdog (write)
0 = disable watchdog (read only)
3-0
RW
0
The nominal timeout period is 20% longer than
the minimum.
0 = 125 msec
1 = 250 msec
2 = 500 msec
3 = 1 sec
4 = 2 sec
5 = 4 sec
6 = 8 sec
7 = 16 sec
8 = 32 sec
9 = 64 sec
10 = 128 sec
11 = 256 sec
12-15 reserved
Table 2-25: Reset Control Register
Bits
Type
Default
Function
7-2
R
0
Reserved
1
RW
1
Reset VGA-AGP interface
1 = set reset signal high
0 = set reset signal low
0
RW
1
Reset the Ethernet chip
1 = set reset signal high
0 = set reset signal low
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