CP302
Functional Description and Configuration
ID 21112, Rev. 05
Page 2 - 37
®
PEP Modular Computers GmbH
2.9.3
Interrupt Configuration Register
The interrupt configuration register holds a series of bits defining the interrupt routing for
the watchdog, the power control derate signal and the CompactPCI enumeration signal.
If the watchdog timer timesout, it can generate three independent hardware events:
reset, SMI and IRQ5 interrupt.
The enumeration signal is generated by a hotswap compatible board after insertion and
prior to removal. The system uses this interrupt signal to force software to configure the
new board. The derate signal indicates that the power supply is beginning to derate its
power output.
The I/O location for the interrupt configuration is 0x284.
Table 2-26: Onboard Interrupt Configuration
Bits
Type
Default
Function
7-5
R
0
Reserved
4
RW
0
CPCI enum signal IRQ5 routing
1 = enable IRQ5
0 = disable IRQ5
3
RW
0
CPCI derate signal IRQ5 routing
1 = enable IRQ5
0 = disable IRQ5
2
RW
0
Watchdog hardware reset
1 = enable reset
0 = disable reset
1
RW
0
Watchdog IRQ5 routing
1 = enable IRQ5
0 = disable IRQ5
0
RW
0
Watchdog SMI routing
1 = enable SMI
0 = disable SMI
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