CP302
CMOS Setup
ID 21112, Rev. 05
Page 4 - 35
®
PEP Modular Computers GmbH
4.14 POST Codes
ISA and PCI POST codes are routed to port address 80H.
Table 4-10: Early POST Codes before System BIOS is Shadowed
POST Code
Action
Reset
RTC & KBC initialization
0CFh
Early CPU Detection
0C0h
Early Chipset initialization
0C1h
Memory presence test: detects memory modules and programs
chipset accordingly
0C6h
L2 Cache sizing test
0C3h
Decompresses Bios
0C5h
Shadows Main Bios and jumps to POST
Table 4-11: Normal POST Codes after System BIOS is Shadowed
POST Code
Action
03h
Set 40h, 72h to 1234h if it was a warm boot
04h
Reserved
05h
SuperIO early programming
Clear Screen
Initializes KBC
06h
Tests whether F000-Segment read/writeable
Detects flash type
07h
Tests CMOS access
If supported: Test if overide key (Insert) pressed during reset
08h
0BEh
--
Programs chipset defaults
09h
Reads CPU ID
Cache initialization if necessary
If supported: Restores CMOS from flash backup if required
0Ah
Initializes interrupt vectors
Copies CMOS to stack
If supported: Checks for dual processor
Table continued on following page
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