12-87
Num-
ber
Name
Boolean
Operand
Description
Steps
F99
P99
Data table
shift-in and
compress
CMPW
PCMPW
S, D1, D2
Transfer “S” to “D1”. Any parts of the data between
“D1” and “D2” that are 0 are compressed, and
shifted in order toward “D2”.
7
F100
P100
Right shift of
multiple bits
(n bits) in a
16-bit data
SHR
PSHR
D, n
Shifts the “n” bits of “D” to the right.
5
F101
P101
Left shift of
multiple bits
(n bits) in a
16-bit data
SHL
PSHL
D, n
Shifts the “n” bits of “D” to the left.
5
F102
P102
Right shift of
n bits in a 32-
bit data
DSHR
PDSHR
D, n
Shifts the “n” bits of the 32-bit data area specified
by (D+1, D) to the right.
5
F103
P103
Left shift of n
bits in a 32-
bit data
DSHL
PDSHL
D, n
Shifts the “n” bits of the 32-bit data area specified
by (D+1, D) to the left.
5
F105
P105
Right shift of
one hexade-
cimal digit
(4-bit)
BSR
PBSR
D
Shifts the one digit of data of “D” to the right.
3
F106
P106
Left shift of
one hexade-
cimal digit
(4-bit)
BSL
PBSL
D
Shifts the one digit of data of “D” to the left.
3
F108
P108
Right shift of
multiple bits
(n bits)
BITR
PBITR
D1, D2, n
Shifts the “n” bits of data range by “D1” and “D2” to
the right.
7
F109
P109
Left shift of
multiple bits
(n bits)
BITL
PBITL
D1, D2, n
Shifts the “n” bits of data range by “D1” and “D2” to
the left.
7
F110
P110
Right shift of
one word
(16-bit)
WSHR
PWSHR
D1, D2
Shifts the one word of the areas by “D1” and “D2”
to the right.
5
F111
P111
Left shift of
one word
(16-bit)
WSHL
PWSHL
D1, D2
Shifts the one word of the areas by “D1” and “D2”
to the left.
5
F112
P112
Right shift of
one hexade-
cimal digit
(4-bit)
WBSR
PWBSR
D1, D2
Shifts the one digit of the areas by “D1” and “D2” to
the right.
5
Summary of Contents for FP E Series
Page 1: ......
Page 16: ......
Page 17: ...Chapter 1 Functions and Restrictions of the Unit ...
Page 28: ...1 12 ...
Page 29: ...Chapter 2 Specifications and Functions of the Unit ...
Page 37: ...2 9 Circuit diagram C32 Y0 Y1 Y3 Y4 C28 Y0 Y1 Y3 Y4 Y2 Y5 to YF Y2 Y5 to YB ...
Page 48: ...2 20 ...
Page 49: ...Chapter 3 Expansion ...
Page 56: ...3 8 Terminal layout diagram Note The numbers in the connector are for the first expansion ...
Page 61: ...Chapter 4 I O Allocation ...
Page 66: ...4 6 ...
Page 67: ...Chapter 5 Installation and Wiring ...
Page 90: ...5 24 ...
Page 91: ...Chapter 6 High speed counter Pulse Output and PWM Output functions ...
Page 116: ...6 26 ...
Page 121: ...6 31 ...
Page 125: ...6 35 Pulse output diagram ...
Page 131: ...6 41 ...
Page 139: ...6 49 ...
Page 141: ...6 51 ...
Page 144: ...6 54 Program Continued on the next page ...
Page 145: ...6 55 ...
Page 147: ...6 57 Program ...
Page 151: ...Chapter 7 Communication Cassette ...
Page 210: ...7 60 The values of DT50 and DT51 are written in DT0 and 1 of PLC ...
Page 238: ...7 88 ...
Page 239: ...Chapter 8 Self Diagnostic and Troubleshooting ...
Page 247: ......
Page 248: ......
Page 249: ...Chapter 9 Precautions During Programming ...
Page 260: ...9 12 Example 2 Using the CT instruction between JP and LBL instructions ...
Page 268: ...9 20 ...
Page 269: ...Chapter10 Specifications ...
Page 286: ......
Page 287: ...Chapter 11 Dimensions ...
Page 290: ...11 4 11 1 3 Expansion Unit FPG XY64D2T FPG XY64D2P FPG EM1 ...
Page 293: ...Chapter 12 Appendix ...
Page 297: ...12 5 ...
Page 437: ...12 145 12 7 ASCII Codes ...
Page 439: ......
Page 440: ......