Operation Description
2 - 6
OL600e/610e/610e-PS/610e-S
Service Manual, P/N 59271602
2.1
Control Board
The control board consists of a single chip CPU, Program & Font ROMs—one DRAM for the
OL600e, two DRAMs for the OL610e—an EEPROM, a host interface circuit, and a mechanism
driving circuit.
Single Chip CPU
The single chip CPU is a custom CPU (32-bit internal bus, 16-bit external bus, 25.54 MHz
clock with input frequency from a 12.27 MHz clock) which incorporates the MIPS 3000
RISC CPU and its peripheral devices, and has the following functions:
Built-in Device
Function
Chip select controller
Control of ROM, DRAM and I/O device
Bus controller
DRAM controller
DMA controller
Transfer of image data from DRAM to video output port
Parallel interface controller
Control of Centronics parallel interface
Serial interface controller
Control of RS-232C serial interface
Video output port
Control of LED head
LED STB output port
Timer
Generation of various control timing signals
Monitoring of paper running and paper size
Serial I/O port
Control of operator panel, EEPROM, and options
I/O port
Input and output of sensor and motor signals
Program and Font ROM
OL600e/610e
The Program & Font ROM stores the equipment program and various types of fonts.
EPROM or Mask ROM is used for a Program & Font ROM. The mounting location of this
Program & Font ROM varies depending on the type of ROM (for the mounting location, refer
to Section 7.2).
OL610e/PS
The Program ROM & Font ROM store the HP4 emulation program and various types of fonts.
Mask ROM is used for a Program & Font ROM.
