NXP Semiconductors
QN902x
User Manual of QN902x
UM10996
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© NXP Semiconductors N.V. 2018. All rights reserved.
User Manual
Rev 1.3
— 05 November 2018
93 of 128
57.6
-0.08
-0.0799
76.8
0.16
-0.0799
115.2
-0.08
-0.0799
230.4
0.656
-0.0799
Table 69 Generated baud rate error when uartclk = 2MHz
Desired baud rate(kbps)
Oversampling rate = 16
Oversampling rate = 8
error%
error%
1.2
-0.008
0.0025
2.4
0.00
-0.005
4.8
-0.02
0.01
9.6
0.0395
-0.02
14.4
-0.083
0.01
19.2
-0.078
0.04
28.8
-0.0798
-0.0799
38.4
0.16
-0.0799
57.6
-0.087
-0.0799
76.8
0.156
0.16
115.2
0.64
-0.0799
230.4
---
0.6441
12.2.2 Data Format
The UART has a number of available options for data formatting,
which can be set using
CR (control register). The data transfer begins with the start bit. The CR[LEVEL_INV] is
used to define the start and stop conditions. What follows are the data bits. The order in
which the bits are transmitted (MSB or LSB first) is specified by CR[BIT_ORDER]. Next one
is the parity bit, which can be enabled by CR[PEN]. The UART supports the odd and even
parity checks, which can be selected using CR[EPS] The data transmission ends with one
or two stop bits which can be set using CR[STIP2_EN] .
Figure 19.2 shows the timing for a UART transaction without parity bit enabled. Figure
19.3 shows the timing for a UART transaction with parity enabled (PEN = 1).