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NXP Semiconductors

QN902x

User Manual of QN902x

UM10996

All information provided in this document is subject to legal disclaimers.

© NXP Semiconductors N.V. 2018. All rights reserved.

User Manual

Rev 1.3

— 05 November 2018

60 of 128

7-bit slave address and the read/write bit. In the master mode, the slave address should
be put into TXD to send. While in the slave mode, the slave address should be written
into SLAVE_ADDR[6:0], and the bus controller will monitor incoming slave address on the
SDA line to check if the address matches and this is the slave device to be addressed by
the master.

7.2.2

R/nW bit

The last bit following 7-bit slave address after START condition is the R/nW bit in the first
byte. The R/nW bit signal is sent by master device to set the data transfer direction. When
R/nW bit is 0, the I2C bus interface is in the write mode and the data transfer direction is
from master to slave. When R/nW bit is 1, the I2C bus interface is in the read mode and
the data transfer direction is from the slave to the master.

7.2.3

ACK/NACK

After completing the transfer of one-byte, the receiver should send an ACK bit to the
transmitter. The ACK pulse should occur during the 9th clock cycle of the SCL line. The
clock pulse required to transmit the ACK bit master should be generated by the master.

The transmitter should release the SDA line when the ACK clock pulse is received. The
receiver should also drive the SDA line low during the ACK clock pulse so that the SDA
keeps low during the high period of the ninth SCL pulse. The receiver will not drive the
SDA line low during ninth clock cycle if NACK is to be sent.

7.2.4

Data transfer

Once a successful slave addressing has been established, the data transfer can proceed
on a byte-by-byte basis in the direction specified by the R/nW bit sent by the master. Each
transferred byte is followed by an ACK bit on the 9th SCL clock cycle.

7.2.5

Stop or Repeated START signal

When the transfer ends, or is abnormal, the master will generate a STOP signal to abort
the data transfer or generate a Repeated START signal to start a new transfer cycle.

If the master, as the receiving device, does not acknowledge the slave device, the slave
device releases the SDA line for the master to generate a STOP or Repeated START signal.

7.2.6

SCL clock generation in master mode

The SCL is derived from PCLK, with a two-stage clock divider. The first one is a constant
divided by 20, and the second is divided by (SCL 1).

SCL = (PCLK/20)/(SCL 1)

7.3

Master Mode Operation

7.3.1

Master-transmit

The master initiates the data transfer with a START condition, followed by the Slave
Address and R/nW bit. If R/nW is low, the data transfer occurs from the master to the
slave. The ACK/NACK bit is sent by the slave. After the master receives the ACK/NACK bit,

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Summary of Contents for QN902 Series

Page 1: ...QN902x User Manual of QN902x Rev 1 3 05 November 2018 User Manual Document information Info Content Keywords User manual MCU Register Abstract This document is a user manual of QN902x SoC...

Page 2: ...r Manual Rev 1 3 05 November 2018 2 of 128 Contact information For more information please visit http www nxp com Revision history Rev Date Description 1 0 20150715 First version 1 1 20160408 Updated...

Page 3: ...n and development area based on SoC 2 MCU Subsystem The MCU system includes 32 bit ARM Cortex M0 MCU AHB Lite bus system 64kB system memory Clock reset and power management units Two wire debug interf...

Page 4: ...cted to the NVIC and the NVIC prioritizes the interrupts Software can set the priority of each interrupt The NVIC and the Cortex M0 processor core are closely coupled providing low latency interrupt p...

Page 5: ...em Bus The QN902X contains an AHB Lite bus system to allow bus masters to access the memory mapped address space A multilayer AHB bus matrix connects the 2 master bus interfaces to the AHB slaves The...

Page 6: ...01000000 0x01018000 System SRAM 0x10000000 0x1000FFFF System Registers 0x40000000 Watch Dog Timer 0x40001000 Timer0 0x40002000 Timer1 0x40003000 Timer2 0x40004000 Timer3 0x40005000 RTC 0x40006000 USAR...

Page 7: ...se address is 0x40000000 Table 2 Register Map Offset Name Description 000h CRSS Enable clock gating and set block reset 004h CRSC Disable clock gating and clear block reset 008h CMDCR Set clock switch...

Page 8: ...W1 0 GATING_TIMER2 Write 1 to disable timer 2 clock 0 no effect 29 RW1 0 GATING_TIMER1 Write 1 to disable timer 1 clock 0 no effect 28 RW1 1 GATING_TIMER0 Write 1 to disable timer 0 clock 0 no effect...

Page 9: ...ART1 NGATING_UART0 NGATING_SPI1 NGATING_SPI0 NGATING_32K_CLK NGATING_SPI_AHB NGATING_GPIO NGATING_ADC NGATING_DMA NGATING_BLE_AHB NGATING_PWM RSVD DIS_LOCKUP_RST CLR_BLE_RST CLR_DP_RST CLR_DPREG_RST C...

Page 10: ...CLR_WDOG_RST Write 1 to clear Watch Dog reset 7 W1 x CLR_TIMER3_RST Write 1 to clear timer 3 reset 6 W1 x CLR_TIMER2_RST Write 1 to clear timer 2 reset 5 W1 x CLR_TIMER1_RST Write 1 to clear timer 1...

Page 11: ...APB_DIVIDER 1 15 RW 0 USART1_DIV_BYPASS 1 is bypass USART1 Divider 14 12 RW 001b USART1_DIVIDER 2 0 If USART1_DIV_BYPASS is 0 USART1_CLK AHB_CLK 2 USART1_DIVIDER 1 11 RW 1 USART0_DIV_BYPASS 1 is bypas...

Page 12: ...cription 31 0 RW 0 PIN_CTRL 31 0 Please see GPIO MUX Table Table 8 PMCR1 PIN_MUX_CTRL1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FLASH_CTRL_PIN TEST_ENABLE1...

Page 13: ...1_2 UART1_rxd is connected with P1_0 1 UART1_cts is connected with P3_7 UART1_rxd is connected with P2_0 4 RW 0 I2C_PIN_SEL 0 i2c_scl is connected with P2_4 I2c_sda is connected with P2_3 1 i2c_scl is...

Page 14: ...control one GPIO PAD driver ability 0 Low driver 1 High driver Table 11 PPCR0 PAD_PULL_CTRL0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PAD_PULL_CTRL 31 PAD...

Page 15: ...bol Description 31 30 R 0 RSVD Reserved 29 0 RW 2AAAAA AAh PAD_PULL_CTRL 62 32 Every two bit control one GPIO PAD Pull Up or Pull Down 00b High Z 01b Pull down 10b Pull up 11b Reserved Table 13 RCS RS...

Page 16: ...is 0 generate interrupt 15 0 RW 0 IO_WAKEUP_E N 15 0 Control GPIO 0 15 as Wakeup source 0 Disable GPIO x as Wakeup source 1 Enable GPIO x as Wakeup source Table 15 BLESR BLE_STATUS 31 30 29 28 27 26...

Page 17: ...1 30 RW 0 EN_SW_MAP 1 Enable SW ReMap 29 6 R 0 RSVD Reserved 5 R 0 RAM_BIST_FAIL Reserved 4 R 0 RAM_BIST_END Reserved 3 R 0 ROM_BIST_FAIL Reserved 2 R 0 ROM_BIST_END Reserved 1 RW 0 BIST_START Reserve...

Page 18: ...d hardware 30 RW 1 PD_OSC Reserved Must write 1 29 RW 1 PD_BG Reserved Must write 1 28 RW 1 PD_V2I Reserved Must write 1 27 RW 1 PD_BUCK While DC DC enabled write 0 While DC DC disabled write 1 26 RW...

Page 19: ...27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VDD_RCO_SET DIS_OSC DIS_BG DIS_V2I DIS_BUCK DIS_VREG_A DIS_VREG_D DIS_XTAL DIS_XTAL32 DIS_REF_PLL DIS_LO_VCO DIS_LO_PLL DIS_P...

Page 20: ...ch on Rx MIXER power 15 RW 1 DIS_PPF_PKDET LO VCO power control only effective when SEL_PD 0 1 Switch off Rx PPF peak detector power 0 Switch on Rx PPF peak detector power 14 RW 1 DIS_PPF LO VCO power...

Page 21: ...Write 0 after wakeup 0 Normal 1 Sleep 5 RW 0 BD_AMP_EN 1 is Enable comparator of brown out detector It should be set earlier than EN_BD 2us or more 4 RW 0 DVDD12_PMU_SET Write 1 before entering sleep...

Page 22: ...DET1_LG 0 RSVD VT_PKDET2 VT_PKDET3 0 0 1 0 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 1 0 1 1 0 1 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R R RW RW RW RW RW RW RW RW RW RW RW R RW RW Bit Type...

Page 23: ...PD BUCK_ERR_ISEL 1 BUCK_ERR_ISEL 0 BUCK_VBG 1 BUCK_VBG 0 X32SMT_EN X32BP_RES BM_X32BUF 1 BM_X32BUF 0 X32INJ 1 X32INJ 0 X32ICTRL 5 X32ICTRL 4 X32ICTRL 3 X32ICTRL 2 X32ICTRL 1 X32ICTRL 0 1 0 0 0 1 0 0 1...

Page 24: ...e degeneration resistor in the core of 32 768KHz XTAL 9 8 RW 10b BM_X32BUF 1 0 Bias current control of 32 768KHz buffer 00b 100nA 01b 200nA 10b 500nA 11b 600nA 7 6 RW 01 X32INJ 1 0 Select 32 768KHz XT...

Page 25: ...d Write 01b 13 12 RW 1 BUCK_VTHH 1 0 Reserved Write 11b 11 9 RW 010b BUCK_TMOS 2 0 Reserved Write 010b 8 RW 0 BUCK_FC Reserved Write 0 7 RW 1 BUCK_AGAIN Reserved Write 1 6 RW 0 BUCK_ADRES Reserved Wri...

Page 26: ...1 0 RSVD SPEED_UP_TIME 7 SPEED_UP_TIME 6 SPEED_UP_TIME 5 SPEED_UP_TIME 4 SPEED_UP_TIME 3 SPEED_UP_TIME 2 SPEED_UP_TIME 1 SPEED_UP_TIME 0 RSVD CK_DAC_DLY BYPASS_TESTBUF SEL_TEST_EN TESTREG 7 TESTREG 6...

Page 27: ...lect internal reference voltage 7 16 VDD 1000b Select internal reference voltage 8 16 VDD 1001b Select internal reference voltage 9 16 VDD 1010b Select internal reference voltage 10 16 VDD 1011b Selec...

Page 28: ...internal reference voltage 10 16 VDD 1011b Select internal reference voltage 11 16 VDD 1100b Select internal reference voltage 12 16 VDD 1101b Select internal reference voltage 13 16 VDD 1110b Select...

Page 29: ...LEEP_TRIG When it is 1 sleep counter registers of BLE can be reloaded during BLE deep sleep state 3 0 RW 1111b NC 3 0 Reserved ADDITION_CTRL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12...

Page 30: ...RW 0 HALF_LO_OPCUR Write 1 8 RW 0 EN_RXDAC Reserved 7 RW 0 TX_PLL_PFD_DIS TX LO PLL open loop mode 6 RW 0 RX_PLL_PFD_DIS RX LO PLL open loop mode 5 RW 0 CALI_REDUCE Reduce current of PPF dc offset cal...

Page 31: ...ge Ultra low power consumption Two power supply modes supported Five power modes supported Multiple wakeup sources from Deep Sleep 3 2 Power Supply QN902x embeds an LDO and a DC DC converter in order...

Page 32: ...on can be kept at a minimum level In the power down mode the PMU is responsible for detecting the wake up trigger signals switching on different power domains and re startup of the MCU The QN902x supp...

Page 33: ...r event ACTIVE MCU MCU running Power consumption is dependent on MCU activity and chosen clock speed RADIO RF radio RX TX active Transition between different modes controlled by the power mode state m...

Page 34: ...he DEEPSLEEP bit on the Cortex M0 system control register should be set to 1 the PMUENABLE bit of PGCR2 should also be set to 1 and the system clock should be switched to internal 20MHz The MCU s wake...

Page 35: ...3 0x4 0x5 0x6 0x7 AIN0 AIN1 AIN2 AIN3 AIN0 AIN1 AIN2 AIN3 TEMP BATT INBUF_BP 10 bit SAR ADC SCAN_CH_START 3 0 SCAN_CH_END 3 0 Decimation 16MHz 32kHz DECI_EN DECI_DIV 1 0 VREF WCMP_EN WCMP_TH_HI 15 0 W...

Page 36: ...r GND 0x03 b10 AIN3 P0_7 b01 or b11 VCM or GND 0x04 b10 AIN0 P3_0 b10 AIN1 P3_1 0x05 b10 AIN2 P0_6 b10 AIN3 P0_7 0x06 b10 Reserved Reserved Reserved 0x07 b10 BATT battery monitor b01 or b11 VCM or GND...

Page 37: ...he clock divider can be bypassed by setting ADC_DIV_BYPASS 0x4000_00B4 4 Note The maximum ADC clock speed is 1MHz which means that when the source clock is 16MHz the minimum ADC_DIV is 0011b The ADC r...

Page 38: ...nerated If the result in FIFO is not read out in time and overflow occurs a FIFO overflow interrupt signal is generated As already stated the ADC is a differential ADC The positive maximum value of 20...

Page 39: ...ADC2 ADC Control Register 2 00Ch SR ADC Status Register 010h DATA ADC Data Register 4 3 2 Register Description Table 28 ADC0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5...

Page 40: ...es 16 RW 0 SCAN_EN Scan mode enable 0 Disable 1 Enable 15 RW 0 SINGLE_EN Single mode enable 0 Disable 1 Enable 14 12 RW 0 START_SEL 2 0 ADC conversion trigger sources 000b Software Start 001b Timer0 o...

Page 41: ...RW RW Bit Type Reset Symbol Description 31 RW 0 INT_MASK Enable of ADC interrupt 0 Disable 1 Enable 30 RW 0 DAT_RDY_EN Enable of ADC output data ready interrupt 0 Disable 1 Enable 29 RW 0 WCMP_EN Enab...

Page 42: ...RW 0 WCMP_EN Enable of window compare 0 Disable 1 Enable 3 RW 0 RSVD Reserved 2 1 RW 00b DECI_DIV 1 0 ADC decimation rate 00b 64 01b 256 10 b 1024 11b RSVD 0 RW 0 DECI_EN Enable of decimation 0 Disab...

Page 43: ...R R R R R R R R R R R R R R R R R R R R R R R RW1 RW1 R Bit Type Reset Symbol Description 31 3 RW 0 RSVD Reserved 2 RW1 0 FIFO_OF_IF FIFO overflow interrupt flag write 1 to clear 1 RW1 0 WCMP_IF_IF W...

Page 44: ...uctors QN902x User Manual of QN902x UM10996 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2018 All rights reserved User Manual Rev 1 3 05 November 20...

Page 45: ...tors integrated in QN902x which supports many features and are easily configured to use 5 1 Features The main features of Analog Comparator are as follows Input pins multiplexed with I O pins Input pi...

Page 46: ...below 5 3 Comparator Operation 5 3 1 Comparator Inputs Depending on the comparator operating mode the input to the comparator negative pin may be from the input pin or an internal configurable voltage...

Page 47: ...an application The QN902x Comparator module has individual control over the enable output polarity hysteresis and negative input selection The negative input can be selected in a variety of voltage l...

Page 48: ...13 16 VDD 1110b Select internal reference voltage 14 16 VDD 1111b Select internal reference voltage 15 16 VDD 27 24 RW 0000b ACMP1 3 0 Comparator 1 reference voltage selection 0000b Select external r...

Page 49: ...MP1 is 0 generate interrupt 15 RW 0 ACMP0_VALUE 0 When ACMP0 is 1 generate interrupt 1 When ACMP0 is 0 generate interrupt 14 RW 0 ACMP0_HYST 1 is Enable hysteresis of analog comparator 0 13 RW 0 ACMP1...

Page 50: ...is responsible for controlling oscillators and clocks The CMU provides the capability to selectably turn on and off the clocks to peripherals in addition to enabling disabling and configuring of all...

Page 51: ...k 32MHz PLL Clcok ADC Clock ADC_CLK_SEL ADC_DIV_BYPASS USART1_DIV_BYPASS USART0_DIV_BYPASS PCLK APB_DIV_BYPASS TIMER_DIV _BYPASS XTAL1_32K XTAL2_32K X32INJ Select external 32kHz clock XINJ Select 32 1...

Page 52: ...the RTC and 32 kHz sleep timer blocks The APB clock is derived from the AHB clock and is used for the registers 6 4 Pin description Table 33 shows pins that are associated with the clock block functi...

Page 53: ...the peripheral clocks 6 5 3 Configure BLE clock The BLE_AHB is clocked by the AHB clock and the BLE clock is derived from the AHB clock They are used for BLE RF block and usually do not need to be con...

Page 54: ...31 RW1 0 GATING_TIMER3 Write 1 to disable timer 3 clock 30 RW1 0 GATING_TIMER2 Write 1 to disable timer 2 clock 29 RW1 0 GATING_TIMER1 Write 1 to disable timer 1 clock 28 RW1 1 GATING_TIMER0 Write 1 t...

Page 55: ...20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NGATING_TIMER_3 NGATING_TIMER_2 NGATING_TIMER_1 NGATING_TIMER_0 NGATING_UART_1 NGATING_UART_0 NGATING_SPI_1 NGATING_SPI_0 NGATING_32K_CLK NGATING_S...

Page 56: ...lear BLE reset 13 W1 x CLR_DP_RST Write 1 to clear datapath reset 12 W1 x CLR_DPREG_RST Write 1 to clear datapath register reset 11 W1 x CLR_SLPTIM_RST Write 1 to clear sleep timer reset 10 W1 x CLR_I...

Page 57: ...Reset Symbol Description 31 30 RW 01b CLK_MUX 1 0 Select system clock source 00b High frequency crystal 16MHz or 32MHz 01b 20MHz internal high frequency 10b 32MHz PLL output 11b 32KHz low speed clock...

Page 58: ...ser Manual Rev 1 3 05 November 2018 58 of 128 APB_CLK AHB_CLK 2 APB_DIVIDER 1 3 RW 0 TIMER_DIV_BYPASS 1 is bypass TIMER Divider 2 0 RW 001b TIMER_DIVIDER 2 0 If TIMER_DIV_BYPASS is 0 TIMER_CLK AHB_CLK...

Page 59: ...line provided by the master device to synchronize the serial data transfer SDA serial data address line used to transmit and receive serial data When the I2C bus is free both the SDA and SCL lines sh...

Page 60: ...aster The transmitter should release the SDA line when the ACK clock pulse is received The receiver should also drive the SDA line low during the ACK clock pulse so that the SDA keeps low during the h...

Page 61: ...write new data into TXD and set WR_EN If ACK_RECV 1 stop the data transfer or re start by setting STOP or START bit After the register is set clear TX_INT interrupt and controller will clock out the...

Page 62: ...ess match interrupt is detected and received R nW 1 send ACK back to master by configuring the ACK_SEND bit in TXD register 3 Write data into TXD to send Then clear SAM_INT to clock out the ACK and TX...

Page 63: ...ock ratio fscl pclk 20 SCL_RATIO 1 The frequency range is pclk 20 pclk1260 The duty ratio is 2 3 23 R 0 RSVD Reserved 22 16 RW 0 SLAVE_ADDR 6 0 7 bit Slave address In slave mode the QN902x processor r...

Page 64: ...ssor after transmitting a byte Table 37 SR Bit Type Reset Symbol Description 31 2 R 0 RSVD Reserved 1 R 0 BUSY I2C busy 0 I2C bus is idle or the I2C interface is using the bus unit busy 1 Set when the...

Page 65: ...SVD Reserved 7 0 RW 0 TXD Data to send Table 39 RXD Bit Type Reset Symbol Description 31 8 R 0 RSVD Reserved 7 0 R 0 RXD 7 0 Data received Table 40 INT Bit Type Reset Symbol Description 31 6 R 0 RSVD...

Page 66: ...iagram of PWM is shown in Figure 8 Figure 8 PWM Block Diagram Two independent but identical PWM channels are available with separate control registers There are two 10 bit prescaler values that are co...

Page 67: ...23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD POL_1 INT_EN_1 PWM_EN_1 RSVD RSVD...

Page 68: ...ed 25 16 RW 0 CH1_PSCL 9 0 PWM channel 1 prescaler Output frequency fclk CH1_PSCL 1 15 10 R 0 RSVD Reserved 9 0 RW 0 CH0_PSCL 9 0 PWM channel 0 prescaler Output frequency fclk CH0_PSCL 1 Table 44 PCP...

Page 69: ...RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD CH1_IF RSVD RSVD RSVD RSVD RSVD RSVD RSVD CH0_IF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R...

Page 70: ...capture interrupt generation Input capture function with programmable noise cancellation Positive or negative edge input capture Asynchronous register access 9 2 Functional Description The block diagr...

Page 71: ...es the monitoring even though this monitoring has nothing to do with the counter If users need to measure the interval between two rising edges the users need to record the counter values in the inter...

Page 72: ...ounter current value register 9 3 2 Register Description Table 47 CR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD...

Page 73: ...SR _SYNC_BUSY CR_SYNC_BUSY RSVD RSVD RSVD CAP_IF RSVD RSVD RSVD SEC_IF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R R R R R R R R R R R R RW1 R R R...

Page 74: ...L 4 SEC_VAL 3 SEC_VAL 2 SEC _VAL 1 SEC _VAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RWH RWH RWH RWH RWH RWH RWH RWH RWH RWH RWH RWH RWH RWH RWH RWH RWH RWH RWH RWH RWH RWH RW...

Page 75: ...R R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Bit Type Reset Symbol Description 31 17 R 0 RSVD Reserved 16 RW 0 CAL_DIR RTC calibration direction indicator 0 forward calibrate 1 backward ca...

Page 76: ...external devices The application software can manage the communication by polling the status flag or using dedicated SPI interrupt Four I O pins may be used for communication DAT data out in 4 wire mo...

Page 77: ...rt 4 modes the timing diagram is the same for master and slave as follows CPOL 0 CPOL 1 SCK SS Cycle Data Out Data In Cycle Data Out Data In CPHA 1 CPHA 0 Data captured at the SCK leading edge Data pr...

Page 78: ...or 4x8 bit FIFO 10 2 6 Interrupt When the SPI interrupt is enabled the following 2 flags will generate an interrupt request 1 RX buffer not empty interrupt RX_FIFO_NEPT_IF flag is set to logic 1 if t...

Page 79: ...SPI_IE SPI general interrupt enable 0 disable 1 enable 10 R 0 RSVD Reserved 9 RW 0 RX_FIFO_NEMT_IE RX buffer not empty interrupt enable 0 disable 1 enable 8 RW 0 TX_FIFO_NFUL_IE TX buffer not full in...

Page 80: ...t Symbol Description 31 0 W 0 TXD TX buffer The width is controlled by BUF_WIDTH If BUF_WIDTH 0 the buffer is a 4x8bit FIFO If BUF_WIDTH 1 it is a 32 bit buffer Table 57 RXD Bit Type Reset Symbol Desc...

Page 81: ...TX buffer empty flag Cleared automatically when data is put into buffer 0 There are data in TX buffer 1 There is not data in TX buffer 2 R 0 RSVD Reserved 1 R 0 RX_FIFO_NEPT_IF RX buffer not empty fl...

Page 82: ...nput capture timer mode Input capture event mode Input capture counter mode Compare interrupt Input capture interrupt Programmable PWM waveform generation Pulse width duty and period measurement Input...

Page 83: ...me as the counter value is copied into the CCR register If the interrupt is enabled by register bit ICIE the input capture flag will generate an interrupt to the MCU To improve the noise immunity on t...

Page 84: ...PWM waveform is generated when PWM output enable bit pwm_oe is set The duty and period of the PWM waveform can be controlled by TOPR CCR and POL TCR 14 registers 11 3 2 Input Capture Timer mode The c...

Page 85: ...ly increments and compares its value with TOP register Once the ECNT equals to the TOP register the input capture flag ICF will be asserted The input capture interrupt will be generated if the ICIE is...

Page 86: ...tion 31 30 R 0 RSVD Reserved 29 28 RW 10b CSS clock sources selection 00b external input clock 01b reserved 10b 11b Clk_timer prescaler clock 27 26 R 0 RSVD Reserved 25 16 RW 3FFh PSCL prescaler facto...

Page 87: ...nterrupt enabled 0 RW 1 TEN Timer enable 0 disable 1 enable Table 62 IFR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD R...

Page 88: ...RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD ICER 15 ICER 14 ICER 13 ICER 12 ICER 11 ICER 10 ICER 9 ICER 8 ICER 7 ICER 6 ICER 5 ICER 4 ICER 3 ICER 2 ICER 1 ICER 0 0 0 0 0 0 0...

Page 89: ...CNT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TCNT 31 TCNT 30 TCNT 29 TCNT 28 TCNT 27 TCNT 26 TCNT 25 TCNT 24 TCNT 23 TCNT 22 TCNT 21 TCNT 20 TCNT 19 TCNT...

Page 90: ...y buffer overrun and framing error detection Transmit and receive interrupts Support for Direct Memory Access DMA Line break generation and detection Configurable start and stop bit levels 8 bit paylo...

Page 91: ...g data and noise TXD Transmit Data Output is the serial data output When the transmitter is disabled the output pin returns to its I O port configuration When the transmitter is enabled and nothing is...

Page 92: ...sing a 6 bit UARTFBRD Register is equal to 1 64 100 1 56 This occurs when m 1 and the error cumulates over 64 clock ticks Below table lists the errors for typical baud rates Table 67 Generated baud ra...

Page 93: ...56 0 16 115 2 0 64 0 0799 230 4 0 6441 12 2 2 Data Format The UART has a number of available options for data formatting which can be set using CR control register The data transfer begins with the st...

Page 94: ...ility of a receive buffer overwrite error due to the long interrupt latency The auto flow mode can be used in two ways full auto flow automating both nCTS and nRTS and half auto flow automating only n...

Page 95: ...e routine They must be cleared manually by software allowing the software to determine the cause of the UART0 1 interrupt transmit complete or receive complete The UART_INT will be auto cleared by sof...

Page 96: ...s document is subject to legal disclaimers NXP Semiconductors N V 2018 All rights reserved User Manual Rev 1 3 05 November 2018 96 of 128 Start Configure UART_TXD Configure UART_BAUD End Y N Cts_en 1...

Page 97: ...18 All rights reserved User Manual Rev 1 3 05 November 2018 97 of 128 The read operation consists of the following steps 1 Configure UART_BAUD 2 Configure UART_CR 3 Receive data after detecting valid...

Page 98: ...to legal disclaimers NXP Semiconductors N V 2018 All rights reserved User Manual Rev 1 3 05 November 2018 98 of 128 Start End Config ure UART_CR Another data is received N Y Start bit is detected N Y...

Page 99: ...n 000h UART_TXD Tx data register 004h UART_RXD Rx data register 008h UART_BAUD 0x00000403 Baud rate register 00Ch UART_CR 0x00000880 Control register 010h UART_FLAG 0x00000000 Status register 12 3 2 R...

Page 100: ...bled 15 12 RW 0 RSVD Reserved 11 RW 1 OVS Oversampling rate 1 indicates oversampling rate is 16 0 indicates oversampling rate is 8 10 RW 0 CTS_EN CTS hardware flow control enable 0 CTS hardware flow c...

Page 101: ...transmission it completes the current character before stopping 1 Transmit is enabled 0 RW 0 UART_EN UART enable 0 UART is disabled If the UART is disabled in the middle of transmission or reception...

Page 102: ...ad 0 No Framing error interrupt 1 The received data does not have a valid stop bit 2 RW1 0 OE_INT Overrun error interrupt status Write 0 Invalid 1 Clear this interrupt Read 0 No overrun error interrup...

Page 103: ...each positive clock edge of WDOGCLK when the clock enable WDOGCLKEN is HIGH The watchdog monitors the interrupt and asserts a reset WDOGRES signal when the counter reaches 0 and the counter is stoppe...

Page 104: ...OAD 24 LOAD 23 LOAD 22 LOAD 21 LOAD 20 LOAD 19 LOAD 18 LOAD 17 LOAD 16 LOAD 15 LOAD 14 LOAD 13 LOAD 12 LOAD 11 LOAD 10 LOAD 9 LOAD 8 LOAD 7 LOAD 6 LOAD 5 LOAD 4 LOAD 3 LOAD 2 LOAD 1 LOAD 0 1 1 1 1 1 1...

Page 105: ...and set LOW to disable the counter and interrupt Reloads the counter from the value in WDOGLOAD when the interrupt is enabled and was previously disabled Table 80 Watchdog Clear Interrupt Register WD...

Page 106: ...R R R R R R R R R R R R R R R R R R R R Bit Type Reset Symbol Description 31 1 R 0 RSVD Reserved 0 R 0 MASKINTSTAT Enabled interrupt status from the counter It indicates the masked interrupt status f...

Page 107: ...0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R RW Bit Type Reset Symbol Description 31 1 R 0 RSVD Reserved 0 RW 0 INTEGTESTEN When set HIGH places the watchdog i...

Page 108: ...lity issues All ports have programmable internal pull up pull down high z As output the GPIOs can be individually cleared or set 14 3 Functional Description The GPIO signals operate as either general...

Page 109: ...masked DATAOUT register Only bits set to 1 in the MASK register enable the corresponding bits in the masked registers to be changed or their values to be read Setting any mask bit to 1 allows the pin...

Page 110: ...1_4 GPIO12 RDYN O NC TIMER1_3 I O NC 25 24 P1_5 GPIO13 RADIO_EN O PWM1 O TIMER1_2 I O NC 27 26 P1_6 GPIO14 SPI0_CS1_O O PWM0 O TIMER0_3 I O NC 29 28 P1_7 GPIO15 UART0_RXD I SPI0_DIN I TIMER0_o O Test_...

Page 111: ...on provided in this document is subject to legal disclaimers NXP Semiconductors N V 2018 All rights reserved User Manual Rev 1 3 05 November 2018 111 of 128 GUI of QnDriverTools For more details of Qn...

Page 112: ...h PAD_DRV_CTRL PAD Driver control 30h PAD_PULL_CTRL0 PAD Pull up and Pull down control 0 34h PAD_PULL_CTRL0 PAD Pull up and Pull down control 1 3Ch IO_WAKEUP_CTRL Controller IO as wakeup source 14 4 1...

Page 113: ...le test pin that share with SWD interface 29 RW 0 TEST_ENABLE 0 1 is Enable other 13 test pins 28 0 RW 0h PIN_CTRL 60 32 Please see GPIO MUX Table 14 4 1 3 PIN_MUX_CTRL2 PIN_MUX_CTRL2 Offset 28h 31 30...

Page 114: ...ted with P0_0 SPI 0 Data in is connected with P1_7 1 SPI 0 CLK is connected with P3_5 SPI 0 CS0 is connected with P3_6 SPI 0 Data out is connected with P3_4 SPI 0 Data in is connected with P3_3 0 RW 0...

Page 115: ...0 Offset 30h PMU 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PAD_PULL_CTRL 31 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 RW RW RW RW RW...

Page 116: ...0 1 0 R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Description of Word Bit Type Reset Name Description 31 30 R 0 RSVD 29 0 RW 2AAAAAAAh PAD_PULL_CTRL...

Page 117: ...ith a delay of two cycles 004h DATAOUT Data output Register value 31 0 Write output data Read Current value of data output register 010h OUTENABLESET Output enable set 31 0 Write 1 Set the output enab...

Page 118: ...ter 31 0 Write 1 To clear the interrupt request 0 No effect Read back 31 0 IRQ status Register 400h 7FCh MASKBYTE7TO0 Bits 9 2 of the address value are used as enable bit mask for the access 31 8 Not...

Page 119: ...output Register value Table 89 OUTENABLESET Bit Type Reset Symbol Description 31 0 RW1 0 OUTENABLESET 31 0 Output enable set Table 90 OUTENABLECLR Bit Type Value Symbol Description 31 0 RW1 0 OUTENAB...

Page 120: ...120 of 128 31 0 RW 1 0 INTTYPECLR 31 0 Interrupt type clear Table 95 INTPOLSET Bit Type Reset Symbol Description 31 0 RW1 0 INTPOLSET 31 0 Polarity level edge IRQ configuration Table 96 INTPOLCLR Bit...

Page 121: ...s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of cus...

Page 122: ...igure 1 QN902x MCU subsystem block diagram 3 Figure 2 QN902X System Address Space 6 Figure 3 DC DC Mode 31 Figure 4 LDO mode 32 Figure 5 Power Mode State Machine 33 Figure 6 shows the block diagram of...

Page 123: ...PAD_PULL_CTRL0 14 Table 12 PPCR1 PAD_PULL_CTRL1 14 Table 13 RCS RST_CAUSE_SRC 15 Table 14 IOWCR IO_WAKEUP_CTRL 15 Table 15 BLESR BLE_STATUS 16 Table 16 SMR SYS_MODE_REG 17 Table 17 CHIP_ID 17 Table 1...

Page 124: ...RTCLK 8MHz 92 Table 68 Generated baud rate error when uartclk 4MHz92 Table 69 Generated baud rate error when uartclk 2MHz93 Table 70 UART0 UART1 Register Map 99 Table 71 TXD 99 Table 72 RXD 99 Table 7...

Page 125: ...ment is subject to legal disclaimers NXP Semiconductors N V 2018 All rights reserved User Manual Rev 1 3 05 November 2018 125 of 128 Table 91 INTENSET 119 Table 92 INTENCLR 119 Table 93 INTTYPESET 119...

Page 126: ...ower Control 38 4 3 Register Description 39 4 3 1 Register Map 39 4 3 2 Register Description 39 4 4 Software Document and Example Code 43 5 Comparator 45 5 1 Features 45 5 2 Function Description 46 5...

Page 127: ...s 82 11 2 Functional Description 82 11 2 1 Clock Sources 83 11 2 2 Input Capture Unit 83 11 2 3 Compare Unit 83 11 2 4 PWM Waveform Generation 83 11 3 Operation Modes 84 11 3 1 Free Running mode 84 11...

Page 128: ...ors N V 2018 All rights reserved For more information visit http www nxp com Date of release 05 November 2018 Document identifier UM10996 14 4 1 6 PAD_PULL_CTRL1 116 14 4 1 7 IO_WAKEUP_CTRL 116 14 4 2...

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