NXP Semiconductors
QN902x
User Manual of QN902x
UM10996
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
User Manual
Rev 1.3
— 05 November 2018
12 of 128
25-0
RW
10001
47h
STCALIB[2
5-0]
CPU STCALIB input
Table 7 PMCR0 (PIN_MUX_CTRL0)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PIN_
C
TR
L[31
]
PIN_
C
TR
L[30
]
PIN_
C
TR
L[29
]
PIN_
C
TR
L[28
]
PIN_
C
TR
L[27
]
PIN_
C
TR
L[26
]
PIN_
C
TR
L[25
]
PIN_
C
TR
L[24
]
PIN_
C
TR
L[23
]
PIN_
C
TR
L[22
]
PIN_
C
TR
L[21
]
PIN_
C
TR
L[20
]
PIN_
C
TR
L[19
]
PIN_
C
TR
L[18
]
PIN_
C
TR
L[17
]
PIN_
C
TR
L[16
]
PIN_
C
TR
L[15
]
PIN_
C
TR
L[14
]
PIN_
C
TR
L[13
]
PIN_
C
TR
L[12
]
PIN_
C
TR
L[11
]
PIN_
C
TR
L[10
]
PIN_
C
TR
L[9]
PIN_
C
TR
L[8]
PIN_
C
TR
L[7]
PIN_
C
TR
L[6]
PIN_
C
TR
L[5]
PIN_
C
TR
L[4]
PIN_
C
TR
L[3]
PIN_
C
TR
L[2]
PIN_
C
TR
[1]
PIN_
C
TR
L[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
W
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Bit
Type
Reset
Symbol
Description
31-0
RW
0
PIN_CTRL[31-0]
Please see GPIO MUX Table;
Table 8 PMCR1 (PIN_MUX_CTRL1)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FL
A
SH_C
TR
L_P
IN
TES
T_E
NA
BLE1
TES
T_E
NA
BLE0
PIN_
C
TR
L[60
]
PIN_
C
TR
L[59
]
PIN_
C
TR
L[58
]
PIN_
C
TR
L[57
]
PIN_
C
TR
L[56
]
PIN_
C
TR
L[55
]
PIN_
C
TR
L[54
]
PIN_
C
TR
L[53
]
PIN_
C
TR
L[52
]
PIN_
C
TR
L[51
]
PIN_
C
TR
L[50
]
PIN_
C
TR
L[49
]
PIN_
C
TR
L[48
]
PIN_
C
TR
L[47
]
PIN_
C
TR
L[46
]
PIN_
C
TR
L[45
]
PIN_
C
TR
L[44
]
PIN_
C
TR
L[43
]
PIN_
C
TR
L[42
]
PIN_
C
TR
L[41
]
PIN_
C
TR
L[40
]
PIN_
C
TR
L[39
]
PIN_
C
TR
L[38
]
PIN_
C
TR
L[37
]
PIN_
C
TR
L[36
]
PIN_
C
TR
L[35
]
PIN_
C
TR
L[34
]
PIN_
C
TR
L[33
]
PIN_
C
TR
L[32
]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Bit
Type
Reset
Symbol
Description
31
RW
0
FLASH_CTRL_PIN
When External Flash is used,
0 = P1_0,P1_1,P1_2,P1_3 port is for SPI Flash;
1 = P1_0,P1_1,P1_2,P1_3port is
n’t for SPI Flash;
30
RW
0
TEST_ENABLE1
Reserved. Must write 0.
29
RW
0
TEST_ENABLE0
Reserved. Must write 0.
28-0
RW
0
PIN_CTRL[60-32]
Please see GPIO MUX Table;
Table 9 PMCR2 (PIN_MUX_CTRL2)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0