NXP Semiconductors
QN902x
User Manual of QN902x
UM10996
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© NXP Semiconductors N.V. 2018. All rights reserved.
User Manual
Rev 1.3
— 05 November 2018
84 of 128
11.3
Operation Modes
The operation mode and the behavior of the Timer is defined by the Operation Mode
Select bits (OMS[1:0]).
summarizes the supported modes of the 32/16 bit
timers.
Table 59 Operation Modes
Mode
OMS[1]
OMS[0]
Mode of Operation
0
0
0
Free Running mode
1
0
1
Input Capture Timer mode
2
1
0
Input Capture Event mode
3
1
1
Input Capture Count mode
11.3.1
Free Running mode
In this mode, the counter will count from zero to the value stored in the TOP Buffer and
then restart from zero. Whenever the counter reaches the value of the TOP Buffer, the
Timer Overflow flag (TOV) will be set and an interrupt will be generated if the interrupt
is enabled by the register bit (OVIE).
The comparison of TCNT and CCR buffer is always active in this mode. Once TCNT equals
to CCR buffer, the Output Compare Flag (OCF) is asserted, and a compare match
interrupt is generated if compare interrupt (OCIE) is enabled.
The PWM waveform is generated when PWM output enable bit (pwm_oe) is set. The
duty and period of the PWM waveform can be controlled by TOPR, CCR and
POL(TCR[14]) registers.
11.3.2
Input Capture Timer mode
The capture timer mode is used to capture the trigger events, and record the time-
stamp in the CCR. It can be used to calculate the pulse width, the period and the duty.
In this mode, the counter will count from zero and will reset to zero at specified edge of
the input capture signal, which is set by ICCLR(TCR[7] . The level change on the Input
Capture Pin (ICP) will trigger the capture event. The triggering operation is defined by
the Input Capture Edge Select bits (ICES[1:0]).
If the a trigger event occurs happens, the Input Capture Flag (ICF) will be set at the clock
cycle. At the same time, the current counter value will be copied to the CCR, and an
interrupt will be generated if the Input Capture Interrupt Enable bit (ICIE) is set.
11.3.3
Input Capture Event mode
This mode is used to count the number of events during a period defined by the TOP
register. When the event happens, the counter ECNT will be incremented. At the end of
the specified period, an Overflow flag (TOV) will be asserted and the value of ECNT will
be copied to the register ICETR. The timer counter TCNT and event counter ECNT will be
reset to zero and begin a new event counting.