NXP Semiconductors
QN902x
User Manual of QN902x
UM10996
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
User Manual
Rev 1.3
— 05 November 2018
47 of 128
The input pins to the comparator are multiplexed with I/O pins, must be
enabled as analog input by control bit AINx_EN before using it as comparator
input.
5.3.2
Comparator Outputs
The output of comparator are routed to three peripherals: Timer, Interrupt
Controller, Wakeup Source Controller.
When timer working in Capture mode, the comparator output can be used to
trigger the Timer capture operation. The ICSS bit of Timer TCR register is used
to enable the input to Timer. Once enabled, the output of Comparator 0 is
connected with Timer0 and Timer 2, while output of Comparator 1 is
connected with Timer 1 and Timer 3.
5.3.3
Comparator Configuration
The comparator module provides a flexible configuration to allow the module to
be tailored to the needs of an application. The QN902x Comparator module has
individual control over the enable, output polarity, hysteresis and negative
input selection. The negative input can be selected in a variety of voltage level
when configured as using internal reference.
5.4
Register Description
The Analog Comparator Control register base address is 0x400000b8.
5.4.1
Register Description
ANALOG_CTRL
Description of Word
Bit
Type
Reset
Name
Description
31-28
RW
0000b
ACMP0[3-0]
Comparator 0 reference voltage selection 0000b =
Select external reference voltage
0001b = Select internal reference voltage (1/16
VDD)
0010b = Select internal reference voltage (2/16
VDD)
0011b = Select internal reference voltage (3/16
VDD)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
A
C
M
P0
[3]
A
C
M
P0
[2]
A
C
M
P0
[1]
A
C
M
P0
[0]
A
C
M
P1
[3]
A
C
M
P1
[2]
A
C
M
P1
[1]
A
C
M
P1
[0]
BD[
1]
BD[
0]
EN
_A
C
M
P0
EN
_A
C
M
P1
EN_BT
EN_BD
EN_TS
A
C
M
P1
_VA
LU
E
A
C
M
P0
_VA
LU
E
A
C
M
P1
_HY
ST
A
C
M
P2
_HY
ST
A
IN3_
EN
A
IN2_
EN
A
IN1_
EN
A
IN0_
EN
BUC
K_PM
D
R
BUC
K_NM
D
R
PA
_GA
IN[4]
XS
P_
C
SEL
SL
EE
P_
TR
IG
NC
[3
-0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW