NXP Semiconductors QN902 Series, User Manual

Page: 113 / 128

NXP Semiconductors
QN902x
User Manual of QN902x
UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
User Manual Rev 1.3
— 05 November 2018
113 of 128
FL
A
SH_PIN_
C
TR
L
TES
T_E
NA
BLE
PIN_
C
TR
L[60
-32]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R
W
RW
Description of Word
Bit Type Reset Symbol Description
31 RW 0 FLASH_PIN_CTRL When External Flash is used,
0 = P1_0,P1_1,P1_2,P1_3 port is for SPI Flash;
1 = P1_0,P1_1,P1_2,P1_3 port isn’t for SPI Flash;
30 RW 0 TEST_ENABLE[1] 1 is Enable test pin that share with SWD interface;
29 RW 0 TEST_ENABLE[0] 1 is Enable other 13 test pins;
28-0 RW 0h PIN_CTRL[60-32] Please see GPIO MUX Table;
14.4.1.3 PIN_MUX_CTRL2
PIN_MUX_CTRL2 Offset = 28h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1 0
TES
T_C
TR
L[4
:0]
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
C
LK_O
U
T_S
EL
U
A
R
T1_
PIN_
SEL
I2C
_P
IN_S
EL
A
D
C
T_P
IN_S
EL
R
SVD
SPI0_
PIN_
SEL
SPI1_
PIN_
SEL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
RW RW RW RW RW
R R R R R R R R R R R R R R R R R R R
RW RW RW RW RW
R
RW RW
Description of Word
Bit Type Reset Name Description
31-27 RW 0 TEST_CTRL[4 :0] Control Test Pin source;
26-8 R 0 RSVD Reserved
7 RW 1 CLK_OUT_SEL[1] 0 = CLKOUT1 is HCLK;
1 = CLKOUT1 is CLK_32K
6 RW 0 CLK_OUT_SEL[0] 0 = CLKOUT0 is HCLK;
1 = CLKOUT0 is CLK_32K